公开(公告)号：EP0826152A4

公开(公告)日：1998-12-23

申请号：EP96915407

申请日：1996-04-30

Applicant: MICRON TECHNOLOGY INC

Inventor： WOOD ALAN G ,  FARNWORTH WARREN M ,  AKRAM SALMAN ,  HEMBREE DAVID R

IPC: G01R31/26 ,  G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  G01R31/02

CPC classification number: G01R1/07314 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.

Abstract translation: 用于测试未封装半导体晶片的方法和装置包括安装在母板（10）上的母板（10）和多个互连（12），并适于建立与芯片（14）的临时电连接。 互连（12）可以形成有用于接触管芯（14）的接合焊盘（22）的硅衬底（20）和凸起的接触构件（16）。 或者，互连（16）可以形成有安装在绝缘膜（74）上的微凸块接触构件（16）。 母板（10）允许每个模具（14）单独测试速度和功能，并且还可以使用标准老化炉并行测试。 在替代实施例中，使用母板/子板布置进行测试。 每个子板（82）包括允许骰子（14）单独测试速度和功能的互连（12）。 然后可以将多个子板（82）安装到母板（10）上，以使用标准老化烤箱进行老化测试。

公开(公告)号：EP1018023A4

公开(公告)日：2003-07-23

申请号：EP98908647

申请日：1998-02-11

Applicant: MICRON TECHNOLOGY INC

Inventor： HEMBREE DAVID R ,  FARNWORTH WARREN M ,  AKRAM SALMAN ,  WOOD ALAN G ,  DOHERTY C PATRICK ,  KRIVY ANDY J

IPC: G01R1/073 ,  G01R31/28 ,  G01R31/316

CPC classification number: G01R1/073 ,  G01R31/2886

Abstract: A probe card (10) for testing semiconductor wafers (12), and a method and system (82) for testing wafers (12) using the probe card (10) are provided. The probe card (10) includes an interconnect substrate (16) having contact members (20) for establishing electrical communication with contact locations (15) on the wafer (12). The probe card (10) also includes a membrane (18) for physically and electrically connecting the interconnect substrate (16) to the testing apparatus (78), and a compressible member (28) for cushioning the pressure exerted on the interconnect substrate (16) by the testing apparatus (78).

Abstract translation: 探针卡（10）用于半导体晶片（12）的测试，半导体晶片（12）具有多个具有多个接触位置的半导体晶片。 晶圆支撑电路朝上，与探头接触。 探针卡包括互连衬底（16）和膜（18）。 衬底包括被配置为接触半导体晶片的接触位置的接触构件（20）的图案。 膜将互连基板物理和电连接到安装到测试端口的探针卡夹具（22）。 膜安装板（24）将膜固定到固定装置上。 力施加机构（32）和弹簧加载力施加构件（34）与卡相关联。