Abstract:
A semiconductor component includes a semiconductor substrate having at least one conductive interconnect on the backside thereof bonded to an inner surface of a substrate contact. A stacked semiconductor component includes multiple semiconductor components in a stacked array having bonded connections between conductive interconnects on adjacent components. An image sensor semiconductor component includes a semiconductor substrate having light detecting elements on the circuit side, and conductive interconnects on the backside.
Abstract:
A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.
Abstract:
Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.
Abstract:
A probe card (10) for testing semiconductor wafers (12), and a method and system (82) for testing wafers (12) using the probe card (10) are provided. The probe card (10) includes an interconnect substrate (16) having contact members (20) for establishing electrical communication with contact locations (15) on the wafer (12). The probe card (10) also includes a membrane (18) for physically and electrically connecting the interconnect substrate (16) to the testing apparatus (78), and a compressible member (28) for cushioning the pressure exerted on the interconnect substrate (16) by the testing apparatus (78).
Abstract:
A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.
Abstract:
A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.