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    ARRAY SUBSTRATE AND PREPARATION METHOD THEREFOR, AND DISPLAY DEVICE
    5.
    发明公开
    ARRAY SUBSTRATE AND PREPARATION METHOD THEREFOR, AND DISPLAY DEVICE 有权
    ARRAYSUBSTRAT UND HERSTELLUNGSVERFAHRENDAFÜRUND ANZEIGEVORRICHTUNG

    公开(公告)号：EP3073522A4

    公开(公告)日：2017-06-28

    申请号：EP14859300

    申请日：2014-07-25

    申请人： BOE TECHNOLOGY GROUP CO LTD

    发明人： LIU XIANG

    IPC分类号： H01L27/12 ,  H01L21/027 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

    CPC分类号： H01L27/1288 ,  H01L21/02565 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/441 ,  H01L21/469 ,  H01L21/47573 ,  H01L21/47635 ,  H01L21/56 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/127 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An array substrate, a manufacturing method thereof, and a display device are provided, which are related to a display technology filed. The method includes: forming a pattern layer (201a) including a pixel electrode (20), and a pattern layer including a gate electrode (30) and a gate line on a base substrate (10) through one patterning process; on the substrate (10) with the pattern layer including the gate electrode (30) and the gate line formed thereon, forming a gate insulating layer (401), a pattern layer at least including a metal oxide semiconductor active layer (50) and a pattern layer at least including an etch stop layer (601) through one patterning process or two patterning processes; wherein, a first via hole (71) for exposing the pixel electrode (20) is formed over the pixel electrode (20); on the substrate (10) with the etch stop layer (601) formed thereon, forming a pattern layer including a source electrode (80a), a drain electrode (80b) and a data line through one patterning process; wherein, the source electrode (80a) and the drain electrode (80b) each contact a metal oxide semiconductor active layer (50), and the drain electrode (80a) is electrically connected to the pixel electrode (20) through the first via hole (71).

    摘要翻译： 提供了一种阵列基板及其制造方法和显示装置，与显示技术领域相关。 该方法包括：通过一次构图工艺在衬底基板（10）上形成包括像素电极（20）的图形层（201a）以及包括栅电极（30）和栅线的图形层; 在具有包括栅极电极30和形成在其上的栅极线的图案层的衬底10上形成栅极绝缘层401，至少包括金属氧化物半导体活性层50和图案化层50的图案层， 通过一个构图工艺或两个构图工艺至少包括蚀刻停止层（601）的图案层; 其中，在像素电极（20）上形成用于暴露像素电极（20）的第一通孔（71）; 在其上形成有蚀刻停止层（601）的衬底（10）上，通过一次构图工艺形成包括源电极（80a），漏电极（80b）和数据线的图形层; 其中，所述源电极80a和所述漏电极80b分别与金属氧化物半导体有源层50接触，所述漏电极80a通过所述第一过孔电连接所述像素电极20， 71）。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    6.
    发明公开
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：EP3301703A1

    公开(公告)日：2018-04-04

    申请号：EP17188984.3

    申请日：2017-09-01

    申请人： Semiconductor Manufacturing International Corporation (Beijing) ,  Semiconductor Manufacturing International Corporation (Shanghai)

    发明人： ZHOU, Ming

    IPC分类号： H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

    CPC分类号： H01L29/1606 ,  H01L21/02488 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/469 ,  H01L21/76861 ,  H01L21/76876 ,  H01L21/823431 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/1037 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78684 ,  H01L45/06

    摘要： The present invention relates to the technical field of semiconductor technologies and discloses a semiconductor device and a manufacturing method therefor. The method includes forming a growth substrate by providing a substrate structure containing a sacrificial substrate, a first dielectric layer on the sacrificial substrate, and a plurality of recesses formed through the first dielectric layer and into the sacrificial substrate, by forming a buffer layer covering exposes surfaces of the plurality of recesses, by selectively growing a graphene layer on the buffer layer, and by filling the plurality of recesses with a second dielectric layer. The method further includes attaching the growth substrate to a bonding substrate such that the second dielectric layer attaches to the bonding substrate; removing the sacrificial substrate; and removing the buffer layer so as to expose the graphene layer. The method of present invention avoids adverse effects from patterning graphene by using selective growth of graphene on a patterned buffer layer.

    摘要翻译： 本发明涉及半导体技术的技术领域，并且公开了一种半导体器件及其制造方法。 该方法包括通过提供包含牺牲基板，牺牲基板上的第一介电层以及穿过第一介电层形成并进入牺牲基板的多个凹槽的基板结构，通过形成覆盖曝光的缓冲层来形成生长基板 通过在缓冲层上选择性生长石墨烯层，并且通过用第二介电层填充多个凹槽来形成多个凹槽的表面。 该方法还包括将生长衬底附接到接合衬底，使得第二电介质层附接到接合衬底; 去除牺牲衬底; 并去除缓冲层以暴露石墨烯层。 本发明的方法通过在图案化的缓冲层上使用石墨烯的选择性生长来避免图案化石墨烯的不利影响。

    Metallic contacts to compound semiconductor devices
    7.
    发明公开
    Metallic contacts to compound semiconductor devices 失效
    Metallische KontaktefürMischhalbleiteranordnungen。

    公开(公告)号：EP0045644A2

    公开(公告)日：1982-02-10

    申请号：EP81303521.9

    申请日：1981-07-31

    申请人： Santa Barbara Research Center

    发明人： Cockrum, Charles A. ,  Chia, Joan K. ,  Kreider, James F.

    IPC分类号： H01L29/40

    CPC分类号： H01L21/02186 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/28575 ,  H01L21/31679 ,  H01L21/31687 ,  H01L21/443 ,  H01L21/469 ,  H01L23/53209 ,  H01L29/45 ,  H01L29/452 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Metallic contacts to compound semiconductor devices which employ a native oxide for passivation are provided. The metallic contacts of the invention comprise at least two metal layers: a first layer making non-rectifying contact with the semiconductor surface and providing a diffusion barrier and a second layer thereon comprising an easily oxidizable metal. A low resistivity metal layer may optionally be interposed between the two metal layers for improved conductivity.
    The metallic contact is formed prior to passivation. The diffusion barrier layer prevents diffusion of potentially deleterious materials into the semiconductor, while exposed portions of the oxidizable metal form an insulating oxide during anodic passivation in an electrolyte. The insulating oxide prevents disruption of the electric field distribution in the electrolyte, thereby eliminating passivating oxide and device non-uniformities commonly encountered in the formation of prior art metallic contacts and providing more uniform semiconductor oxide thickness.

    摘要翻译： 提供了使用钝化的自然氧化物的化合物半导体器件的金属接触。 本发明的金属触点包括至少两个金属层：与半导体表面进行非整流接触并提供扩散阻挡层的第一层和在其上的包含易氧化金属的第二层。 可以可选地在两个金属层之间插入低电阻率金属层，以改善导电性。 在钝化之前形成金属接触。 扩散阻挡层防止潜在的有害材料扩散到半导体中，而在电解质中的阳极钝化期间，可氧化金属的暴露部分形成绝缘氧化物。 绝缘氧化物防止电解质中的电场分布的破坏，从而消除在现有技术的金属触点的形成中通常遇到的钝化氧化物和器件不均匀性，并提供更均匀的半导体氧化物厚度。