-
公开(公告)号：KR1020030026855A
公开(公告)日：2003-04-03
申请号：KR1020020056450
申请日：2002-09-17
Applicant: 르네사스 일렉트로닉스 가부시키가이샤
IPC: H05K3/10
CPC classification number: H01L24/97 , H01L23/49822 , H01L23/49838 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05599 , H01L2224/0603 , H01L2224/32225 , H01L2224/32237 , H01L2224/45099 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2224/83385 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/15153 , H01L2924/181 , H01L2924/19043 , H05K1/113 , H05K1/116 , H05K3/064 , H05K3/184 , H05K3/423 , H05K2201/0394 , H05K2201/09563 , H05K2201/09736 , H05K2201/09745 , H05K2203/0369 , H05K2203/0574 , Y10T29/49155 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
Abstract: PURPOSE: To solve the problem wherein a bonding agent is crowed out from a conductive land when an electronic component mounted on the conductive land using a conductive bonding material having viscosity is reduced in size. CONSTITUTION: On the main surface of an insulation substrate 11, a wiring substrate 10 includes the conductive land 12 formed thicker in the peripheral area than the central area, and an electronic component 14 which is electrically mounted on the central area of the conductive land 12 via a conducive bonding material 15.
Abstract translation: 目的：为了解决使用粘度降低的导电性接合材料，在安装在导电性接地面上的电子部件的情况下，从导电性接合面挤出接合剂的问题。 构成：在绝缘基板11的主表面上，布线基板10包括在比中央区域更周边的区域中形成的导电焊盘12，以及电气部件14，电子部件14电连接于导体焊盘12的中心区域 通过有利的接合材料15。
-
公开(公告)号：KR101207273B1
公开(公告)日：2012-12-03
申请号：KR1020100086430
申请日：2010-09-03
Applicant: 에스케이하이닉스 주식회사
Inventor： 윤여송
IPC: H01L23/043 , H01L23/48 , H01L23/12
CPC classification number: H01L23/5389 , H01L23/49827 , H01L24/02 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/105 , H01L2224/02379 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/0401 , H01L2224/05548 , H01L2224/0556 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1329 , H01L2224/133 , H01L2224/16105 , H01L2224/16145 , H01L2224/16238 , H01L2224/2731 , H01L2224/27334 , H01L2224/32057 , H01L2224/32145 , H01L2224/32237 , H01L2224/73204 , H01L2224/73253 , H01L2224/81193 , H01L2224/81815 , H01L2224/8385 , H01L2224/9211 , H01L2224/92143 , H01L2225/1035 , H01L2225/1058 , H01L2924/0001 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15153 , H01L2224/81 , H01L2224/83 , H01L2924/0665 , H01L2224/13099 , H01L2224/05552
Abstract: 임베디드패키지및 그형성방법이개시되어있다. 개시된임베디드패키지는, 반도체칩 몸체및 상기반도체칩 몸체의일면상에장착되고상기반도체칩 몸체의측면으로노출되는범프를각각포함하며상기각각의범프들이상호연결되도록적층되는제1,제2반도체칩과, 상기적층된제1,제2반도체칩을감싸는코어층, 상기코어층내부에배치되며상기제1,제2반도체칩의범프들에전기적으로연결되는제1회로패턴, 상기제1반도체칩과인접한상기코어층의제1면에배치되는제2회로패턴, 상기코어층의제1면과대향하는제2면에배치되는제3회로패턴, 상기코어층내부에형성되며상기제1회로패턴과제2회로패턴을전기적으로연결하는제1 비아및 상기제1회로패턴과제3회로패턴을전기적으로연결하는제2비아를포함하는기판을포함하는것을특징으로한다.
-
Patent Agency Ranking
公开(公告)号：KR1020080008208A
公开(公告)日：2008-01-23
申请号：KR1020070021815
申请日：2007-03-06
Applicant: 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
IPC: H01L21/52
CPC classification number: H01L23/3107 , H01L21/76898 , H01L23/49513 , H01L23/49548 , H01L23/49575 , H01L23/66 , H01L24/05 , H01L24/06 , H01L24/12 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2224/04026 , H01L2224/05026 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/06517 , H01L2224/29101 , H01L2224/29111 , H01L2224/29139 , H01L2224/29339 , H01L2224/32237 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48624 , H01L2224/48647 , H01L2224/4911 , H01L2224/73265 , H01L2224/81801 , H01L2224/83365 , H01L2224/83439 , H01L2224/83801 , H01L2224/83851 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0781 , H01L2924/10158 , H01L2924/14 , H01L2924/1461 , H01L2924/15747 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2224/05552 , H01L2924/00015
Abstract: An improved interconnect structure for semiconductor package is provided to improve performance thereof by improving a packing method and an interconnection method. A semiconductor substrate(104) includes an upper surface(106) and a lower surface. One or more device regions are formed on the upper surface. One or more trench openings are formed from the lower surface through the semiconductor substrate to be connected to the device region. A conductive material layer is deposited in at least one trench opening to fill partially the trench opening. A conductive adhesive layer(118) is deposited on the conductive material layer to fill the remaining part of the trench opening. A conductive lead frame is coupled with the lower surface of the semiconductor substrate.
Abstract translation: 提供了一种用于半导体封装的改进的互连结构，以通过改进打包方法和互连方法来提高其性能。 半导体衬底（104）包括上表面（106）和下表面。 一个或多个器件区域形成在上表面上。 从通过半导体衬底的下表面形成一个或多个沟槽开口以连接到器件区域。 导电材料层沉积在至少一个沟槽开口中以部分地填充沟槽开口。 导电粘合剂层（118）沉积在导电材料层上以填充沟槽开口的剩余部分。 导电引线框架与半导体基板的下表面连接。
-
公开(公告)号：KR101642241B1
公开(公告)日：2016-07-22
申请号：KR1020157006916
申请日：2013-08-23
Applicant: 니혼도꾸슈도교 가부시키가이샤
CPC classification number: H05K1/11 , H01L21/563 , H01L23/12 , H01L23/13 , H01L23/145 , H01L23/49894 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L2224/1161 , H01L2224/131 , H01L2224/13113 , H01L2224/16238 , H01L2224/2919 , H01L2224/32237 , H01L2224/73204 , H01L2224/81193 , H01L2224/81385 , H01L2224/81447 , H01L2224/81815 , H01L2224/83102 , H01L2224/83385 , H01L2224/8385 , H01L2924/3512 , H01L2924/3841 , H05K1/111 , H05K3/3436 , H05K3/3452 , H05K2201/09018 , H05K2201/10977 , H05K2203/0594 , H05K2203/0597 , Y02P70/611 , H01L2924/00014 , H01L2924/014
Abstract: 배선기판에있어서, 언더필의충전불량에의한보이드의형성을억제한다. 배선기판은절연성의기층과: 기층에적층된절연층과: 개구부의내측에있어서절연층으로부터돌출된도전성의접속단자를구비한다. 절연층은개구부가형성된제 1 표면과, 개구부의내측에있어서제 1 표면에대해서기층측으로움푹들어간제 2 표면을가진다. 제 2 표면은개구부의내측에있어서제 1 표면에서접속단자에걸쳐서형성된다. 기층에대해서절연층이적층된적층방향을따른평면인절단면에있어서, 제 2 표면에있어서의임의의점에서절연층의외측으로향하는법선과, 그임의의점에서제 1 표면과평행하게접속단자로향하는평행선이이루는각도는 0°보다크고 90°보다작다.
-
公开(公告)号：KR1020150046177A
公开(公告)日：2015-04-29
申请号：KR1020157006916
申请日：2013-08-23
Applicant: 니혼도꾸슈도교 가부시키가이샤
CPC classification number: H05K1/11 , H01L21/563 , H01L23/12 , H01L23/13 , H01L23/145 , H01L23/49894 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L2224/1161 , H01L2224/131 , H01L2224/13113 , H01L2224/16238 , H01L2224/2919 , H01L2224/32237 , H01L2224/73204 , H01L2224/81193 , H01L2224/81385 , H01L2224/81447 , H01L2224/81815 , H01L2224/83102 , H01L2224/83385 , H01L2224/8385 , H01L2924/3512 , H01L2924/3841 , H05K1/111 , H05K3/3436 , H05K3/3452 , H05K2201/09018 , H05K2201/10977 , H05K2203/0594 , H05K2203/0597 , Y02P70/611 , H01L2924/00014 , H01L2924/014
Abstract: 배선기판에있어서, 언더필의충전불량에의한보이드의형성을억제한다. 배선기판은절연성의기층과: 기층에적층된절연층과: 개구부의내측에있어서절연층으로부터돌출된도전성의접속단자를구비한다. 절연층은개구부가형성된제 1 표면과, 개구부의내측에있어서제 1 표면에대해서기층측으로움푹들어간제 2 표면을가진다. 제 2 표면은개구부의내측에있어서제 1 표면에서접속단자에걸쳐서형성된다. 기층에대해서절연층이적층된적층방향을따른평면인절단면에있어서, 제 2 표면에있어서의임의의점에서절연층의외측으로향하는법선과, 그임의의점에서제 1 표면과평행하게접속단자로향하는평행선이이루는각도는 0°보다크고 90°보다작다.
Abstract translation: 在布线板中，由于填充不良而造成的空隙形成受到抑制。 布线基板具有基底绝缘层，层叠在基底层上的绝缘层，以及在开口内侧从绝缘层突出的导电连接端子。 绝缘层具有形成有开口部分的第一表面和在开口部分内相对于第一表面向基层侧凹陷的第二表面。 第二表面形成为在开口内部从第一表面延伸到连接端子。 作为沿层叠方向的平面的切割线，其中绝缘层被层压到基底层，在第二表面上的任意点处指向绝缘层的外侧的法线， 大于0°且小于90°。
-
公开(公告)号：KR1020120023383A
公开(公告)日：2012-03-13
申请号：KR1020100086430
申请日：2010-09-03
Applicant: 에스케이하이닉스 주식회사
Inventor： 윤여송
IPC: H01L23/043 , H01L23/48 , H01L23/12
CPC classification number: H01L23/5389 , H01L23/49827 , H01L24/02 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/105 , H01L2224/02379 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/0401 , H01L2224/05548 , H01L2224/0556 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1329 , H01L2224/133 , H01L2224/16105 , H01L2224/16145 , H01L2224/16238 , H01L2224/2731 , H01L2224/27334 , H01L2224/32057 , H01L2224/32145 , H01L2224/32237 , H01L2224/73204 , H01L2224/73253 , H01L2224/81193 , H01L2224/81815 , H01L2224/8385 , H01L2224/9211 , H01L2224/92143 , H01L2225/1035 , H01L2225/1058 , H01L2924/0001 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15153 , H01L2224/81 , H01L2224/83 , H01L2924/0665 , H01L2224/13099 , H01L2224/05552
Abstract: PURPOSE: An embedded package and a formation method thereof are provided to reduce the length of a signal path for connecting a semiconductor chip to the outside, thereby improving electrical properties of the embedded package. CONSTITUTION: A first semiconductor chip(100A) or a second semiconductor chip(100B) comprises a semiconductor chip body(110) and a bump(160). A bonding pad(120) is arranged on one surface of the semiconductor chip body. A first insulating film(130) is arranged in order to expose the bonding pad on the one surface of the semiconductor chip body. A redistribution line(150) is arrange on a part of the first insulating film and the one surface of the exposed semiconductor chip body. A substrate(200) comprises a core layer(210), first, second, and third circuit patterns(220,230,240), and first and second vias(250,260).
Abstract translation: 目的：提供嵌入式封装及其形成方法以减小用于将半导体芯片连接到外部的信号路径的长度，从而改善嵌入式封装的电性能。 构成：第一半导体芯片（100A）或第二半导体芯片（100B）包括半导体芯片体（110）和凸块（160）。 在半导体芯片主体的一个表面上配置焊盘（120）。 布置第一绝缘膜（130）以暴露半导体芯片主体的一个表面上的焊盘。 再分配线（150）布置在第一绝缘膜的一部分和暴露的半导体芯片主体的一个表面上。 衬底（200）包括芯层（210），第一，第二和第三电路图案（220,230,240）以及第一和第二通孔（250,260）。
-
公开(公告)号：KR100851931B1
公开(公告)日：2008-08-12
申请号：KR1020070021815
申请日：2007-03-06
Applicant: 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
IPC: H01L21/52
CPC classification number: H01L23/3107 , H01L21/76898 , H01L23/49513 , H01L23/49548 , H01L23/49575 , H01L23/66 , H01L24/05 , H01L24/06 , H01L24/12 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2224/04026 , H01L2224/05026 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/06517 , H01L2224/29101 , H01L2224/29111 , H01L2224/29139 , H01L2224/29339 , H01L2224/32237 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48624 , H01L2224/48647 , H01L2224/4911 , H01L2224/73265 , H01L2224/81801 , H01L2224/83365 , H01L2224/83439 , H01L2224/83801 , H01L2224/83851 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0781 , H01L2924/10158 , H01L2924/14 , H01L2924/1461 , H01L2924/15747 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2224/05552 , H01L2924/00015
Abstract: A semiconductor device includes a semiconductor substrate having top and bottom surfaces, the top surface having at least one device region thereon. At least one trench opening is formed through the substrate from the bottom surface and connecting to the device region. A layer of conductive material is deposited in the at least one trench opening and partially fills the trench opening. A layer of conductive adhesive is deposited over the layer of conductive material and fills a remaining portion of the trench opening.
-
-
-
-
-
-
Search Results
7
records
(took 0.01 seconds)
