公开(公告)号：US07948027B1

公开(公告)日：2011-05-24

申请号：US12635662

申请日：2009-12-10

Applicant: Shing-Hwa Renn ,  Cheng-Chih Huang ,  Yung-Meng Huang

Inventor： Shing-Hwa Renn ,  Cheng-Chih Huang ,  Yung-Meng Huang

IPC: H01L29/76

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10885

Abstract: An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.

Abstract translation: 一种嵌入式位线结构，其中，衬底包括具有原始顶表面的绝缘体层和在绝缘体层的原始顶表面上的半导体层，并且位线沿着一侧设置在沟槽的下部 的活跃区域。 位线包括第一部分和第二部分。 第一部分位于绝缘体层内并且位于绝缘体层的原始顶表面下方。 第二部分设置在第一部分上以电连接有源区的半导体层。 绝缘体衬垫设置在位线的第一部分上，位于位线的第二部分与衬底的半导体层之间，与激活区域相反以进行隔离。 STI设置在沟槽内以围绕有源区域进行隔离。

公开(公告)号：US07553723B2

公开(公告)日：2009-06-30

申请号：US11752177

申请日：2007-05-22

Applicant: Cheng-Chih Huang

Inventor： Cheng-Chih Huang

IPC: H01L21/8242

CPC classification number: H01L27/10867

Abstract: A method of manufacturing a memory device. The memory device comprises a trench in a substrate, a capacitor at the low portion of the trench, a collar dielectric layer overlying the capacitor and covering a portion of the sidewall of the trench, and a conductive layer filling a portion of the trench over the capacitor. First, a first mask layer is formed on the conductive layer, wherein a bottom portion of the first mask layer is thicker than the side portion thereof in the trench. A second mask layer is formed on the first mask layer. Next, a portion of the second mask layer in the trench is ion implanted. The unimplanted portion of the second mask layer is removed.

Abstract translation: 一种制造存储器件的方法。 存储器件包括衬底中的沟槽，在沟槽的低部分处的电容器，覆盖电容器并覆盖沟槽的侧壁的一部分的环形电介质层以及填充沟槽的一部分的导电层 电容器。 首先，在导电层上形成第一掩模层，其中第一掩模层的底部比沟槽中的侧部厚。 在第一掩模层上形成第二掩模层。 接下来，离子注入沟槽中的第二掩模层的一部分。 去除第二掩模层的未植入部分。

公开(公告)号：US20090098698A1

公开(公告)日：2009-04-16

申请号：US12336473

申请日：2008-12-16

Applicant: Cheng-Chih Huang

Inventor： Cheng-Chih Huang

IPC: H01L21/336

CPC classification number: H01L27/10841 ,  H01L27/10867 ,  H01L29/945

Abstract: A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.

Abstract translation: 半导体存储器件。 沟槽电容器，设置在衬底的沟槽的下部，沟槽电容器包括填充电极层和围绕填充电极层的套环电介质层。 轴环电介质层的顶部低于填充电极层的顶表面水平。 垂直晶体管设置在沟槽的上部，包括设置在与沟槽相邻的沟槽的一部分中的掺杂区域。 插入在垂直晶体管和沟槽电容器之间的埋入导电层，其中掩埋导电层的横截面为H形。 沟槽电容器和垂直晶体管的掺杂区域通过H形掩埋导电层电连接。

公开(公告)号：US20060175650A1

公开(公告)日：2006-08-10

申请号：US11145862

申请日：2005-06-06

Applicant: Cheng-Chih Huang

Inventor： Cheng-Chih Huang

IPC: H01L21/8244 ,  H01L29/94 ,  H01L21/8234

CPC classification number: H01L27/10876 ,  H01L27/10841

Abstract: Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.

公开(公告)号：US20060134857A1

公开(公告)日：2006-06-22

申请号：US11297237

申请日：2005-12-07

Applicant: Cheng-Chih Huang

Inventor： Cheng-Chih Huang

IPC: H01L21/8242 ,  H01L21/8244

CPC classification number: H01L27/10841 ,  H01L27/10867 ,  H01L29/945

Abstract: A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.

公开(公告)号：US06927123B2

公开(公告)日：2005-08-09

申请号：US10846272

申请日：2004-05-14

Applicant: Cheng-Chih Huang ,  Sheng-Wei Yang ,  Neng-Tai Shih ,  Chen-Chou Huang

Inventor： Cheng-Chih Huang ,  Sheng-Wei Yang ,  Neng-Tai Shih ,  Chen-Chou Huang

IPC: H01L21/02 ,  H01L21/8242 ,  H01L29/94 ,  H01L21/20

CPC classification number: H01L28/40 ,  H01L27/10864 ,  H01L27/10867 ,  H01L29/945

Abstract: A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and the semiconductor substrate to act as an isolation. The capacitor wire and the collar dielectric layer are etched to a predetermined depth, such that a gap is formed between the spacer and the capacitor wire and the collar dielectric layer. Ions are doped into the exposed semiconductor substrate to form an ion doped area acting as a buried strap. The spacer is removed, and an exposed collar dielectric layer is etched below the level of the surface of the capacitor wire, and a groove is formed between the capacitor wire and the trench sidewall to fill with a conducting layer.

Abstract translation: 一种用于在垂直存储单元中形成自对准埋置带的方法。 提供具有沟槽的半导体衬底，在沟槽的底部形成电容器线，并且在电容器布线和半导体衬底之间形成环形电介质层以作为隔离。 电容器线和套环电介质层被蚀刻到预定深度，使得在间隔物和电容器线和套环电介质层之间形成间隙。 将离子掺杂到暴露的半导体衬底中以形成充当掩埋带的离子掺杂区域。 去除间隔物，并且暴露的环形介电层被蚀刻到电容器线的表面的水平面以下，并且在电容器布线和沟槽侧壁之间形成凹槽以填充导电层。

公开(公告)号：US20050124110A1

公开(公告)日：2005-06-09

申请号：US10846272

申请日：2004-05-14

Applicant: Cheng-Chih Huang ,  Sheng-Wei Yang ,  Neng-Tai Shih ,  Chen-Chou Huang

Inventor： Cheng-Chih Huang ,  Sheng-Wei Yang ,  Neng-Tai Shih ,  Chen-Chou Huang

IPC: H01L21/02 ,  H01L21/8242 ,  H01L29/94 ,  H01L21/8234 ,  H01L21/20 ,  H01L21/8244 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC classification number: H01L28/40 ,  H01L27/10864 ,  H01L27/10867 ,  H01L29/945

Abstract: A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and the semiconductor substrate to act as an isolation. The capacitor wire and the collar dielectric layer are etched to a predetermined dept, such that a gap is formed between the spacer and the capacitor wire and the collar dielectric layer. Ions are doped into the exposed semiconductor substrate to form an ion doped area acting as a buried strap. The spacer is removed, and an exposed collar dielectric layer is etched below the level of the surface of the capacitor wire, and a groove is formed between the capacitor wire and the trench sidewall to fill with a conducting layer.

Abstract translation: 一种用于在垂直存储单元中形成自对准埋置带的方法。 提供具有沟槽的半导体衬底，在沟槽的底部形成电容器线，并且在电容器布线和半导体衬底之间形成环形电介质层以作为隔离。 电容器线和套环电介质层被蚀刻到预定的部分，使得在间隔件和电容器线和套环电介质层之间形成间隙。 将离子掺杂到暴露的半导体衬底中以形成充当掩埋带的离子掺杂区域。 去除间隔物，并且暴露的环形介电层被蚀刻到电容器线的表面的水平面以下，并且在电容器布线和沟槽侧壁之间形成凹槽以填充导电层。

公开(公告)号：US20050014331A1

公开(公告)日：2005-01-20

申请号：US10604361

申请日：2003-07-14

Applicant: Sheng-Wei Yang ,  Cheng-Chih Huang ,  Chien-Mao Liao

Inventor： Sheng-Wei Yang ,  Cheng-Chih Huang ,  Chien-Mao Liao

IPC: H01L21/3105 ,  H01L21/311 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/8234

CPC classification number: H01L27/10894 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31612 ,  H01L27/10864

Abstract: The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP) technique to overcome residue problems that used to occur at the transition region or array edge. It might cause capacitor device failure when ATO residue is left on the transition region.

Abstract translation: 本发明提供了一种在垂直MOSFET DRAM阵列中平面化阵列顶部氧化物（ATO）的方法。 与用于EA / ES（蚀刻阵列/蚀刻支持）模块的现有技术的ARC-RIE平面化方法相反，本发明利用化学机械抛光（CMP）技术来克服在过渡区域发生的残留问题， 阵列边缘。 当ATO残留物留在过渡区域时，可能会导致电容器故障。

公开(公告)号：US5054956A

公开(公告)日：1991-10-08

申请号：US517369

申请日：1990-05-01

Applicant: Cheng-Chih Huang

Inventor： Cheng-Chih Huang

IPC: E02D29/14

CPC classification number: E02D29/1409

Abstract: A covering device for detachably shielding an access hole which is provided on the top portion of a conduit box, includes a fixing member having a peripheral wall defining a top opening and a bottom opening and a base protruding inwardly therefrom; a plurality of bolts being fixed on the base of the fixing member; a plurality of supporting members respectively surrounding the bolts and piled up along the same bolts; a suspension member having a peripheral wall defining an upper opening and a lower opening and a bottom plate protruding inwardly therefrom and being supported by the supporting members. The supporting members are being detachable and replaceable so that the wall of suspension member can be raised or lowered thus enabling the cover of conduit hole to be adjusted to a level with a changing road surface.

Abstract translation: 一种用于可拆卸地遮蔽设置在导管箱顶部上的进入孔的覆盖装置，包括：固定构件，其具有限定顶部开口的周壁和从其向内突出的底部开口; 多个螺栓固定在固定构件的基部上; 分别围绕螺栓并沿着相同的螺栓堆积的多个支撑构件; 悬挂构件，其具有限定上开口的周壁和下开口以及从其向内突出并由支撑构件支撑的底板。 支撑构件是可拆卸和可更换的，使得悬挂构件的壁可以升高或降低，从而使导管孔的盖能够被调整到具有不断变化的路面的水平。

公开(公告)号：US07445986B2

公开(公告)日：2008-11-04

申请号：US11499348

申请日：2006-08-03

Applicant: Cheng-Chih Huang

Inventor： Cheng-Chih Huang

IPC: H01L21/8242

CPC classification number: H01L27/10876 ,  H01L27/10841

Abstract: Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.

Abstract translation: 具有垂直晶体管和电容器的存储单元及其制造方法。 存储单元包括具有沟槽的衬底。 电容器设置在沟槽的底部。 第一导电层电耦合到电容器。 第一导电层通过套环电介质层隔离衬底。 沟槽顶部氧化物（TTO）层设置在第一导电层上。 垂直晶体管设置在TTO层上。 垂直晶体管包括设置在沟槽上部侧壁上的栅介电层和设置在沟槽上部的金属栅极。