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    High-throughput interconnect having pipelined and non-pipelined bus transaction modes
    3.
    发明授权
    High-throughput interconnect having pipelined and non-pipelined bus transaction modes 失效
    具有流水线和非流水线总线事务模式的高吞吐量互连

    公开(公告)号：US06317803B1

    公开(公告)日：2001-11-13

    申请号：US08721893

    申请日：1996-09-27

    申请人： Norman J. Rasmussen ,  Gary A. Solomon ,  David G. Carson ,  George R. Hayek ,  Brent S. Baxter ,  Colyn Case

    发明人： Norman J. Rasmussen ,  Gary A. Solomon ,  David G. Carson ,  George R. Hayek ,  Brent S. Baxter ,  Colyn Case

    IPC分类号： G06F1300

    CPC分类号： G06F13/1615 ,  G06F13/161 ,  G06F13/1631

    摘要： A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.

    摘要翻译： 提供了高吞吐量的存储器访问端口。 该端口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构（如PCI或ISA）可能提供更高数据传输速率的功能。 该端口允许内存读取和写入请求流水线，以隐藏内存访问延迟的影响。 特别地，端口允许以非流水线模式（例如由PCI提供）或以流水线模式执行总线事务。 在流水线模式中，允许在第一存储器访问请求和其对应的数据传送之间插入一个或多个附加存储器访问请求。 相比之下，在非流水线模式下，不能在第一存储器访问请求和其对应的数据传输之间插入附加存储器访问请求。

    Low load host/PCI bus bridge
    5.
    发明授权
    Low load host/PCI bus bridge 失效
    低负载主机/ PCI总线桥

    公开(公告)号：US5740385A

    公开(公告)日：1998-04-14

    申请号：US358359

    申请日：1994-12-19

    申请人： George R. Hayek ,  Brian K. Langendorf ,  Aniruddha Kundu ,  Kuljit S. Bains ,  Gary A. Solomon

    发明人： George R. Hayek ,  Brian K. Langendorf ,  Aniruddha Kundu ,  Kuljit S. Bains ,  Gary A. Solomon

    IPC分类号： G06F13/40 ,  G06F13/00

    CPC分类号： G06F13/4027

    摘要： A bridge for coupling a host bus to a peripheral component interconnect (PCI) bus. A controller is used to transfer an address from the host bus while a datapath is used to transfer data from the host bus. The address and data is then transferred to the PCI bus over a set of signal lines coupled to the PCI bus such that each signal line transfers at least a portion of the address as well as at least a portion of data.

    摘要翻译： 用于将主机总线耦合到外围组件互连（PCI）总线的桥。 当使用数据路径从主机总线传输数据时，控制器用于从主机总线传输地址。 然后将地址和数据通过耦合到PCI总线的一组信号线传送到PCI总线，使得每个信号线传送地址的至少一部分以及数据的至少一部分。

    Time-distributed ECC scrubbing to correct memory errors
    7.
    发明授权
    Time-distributed ECC scrubbing to correct memory errors 失效
    时间分配的ECC擦除来纠正内存错误

    公开(公告)号：US5978952A

    公开(公告)日：1999-11-02

    申请号：US777252

    申请日：1996-12-31

    申请人： George R. Hayek ,  Radhakrishnan Venkataraman ,  Jasmin Ajanovic

    发明人： George R. Hayek ,  Radhakrishnan Venkataraman ,  Jasmin Ajanovic

    IPC分类号： G06F11/10 ,  G11C11/403 ,  G06F11/00 ,  G11C29/00

    CPC分类号： G06F11/106 ,  G11C29/52 ,  G06F11/1028 ,  G06F11/1052 ,  G11C2029/0409

    摘要： Error correction circuitry attempts to detect and correct on the fly erroneous words within random access memory (RAM) within a computer system. RAM errors are scrubbed or corrected back in the memory without delaying the memory access cycle. Rather, the address of the section or row of RAM that contains the correctable error is latched for later used by an interrupt-driven firmware memory-error scrub routine. This routine reads and rewrites each word within the indicated memory section--the erroneous word is read, corrected on-the-fly as it is read, and then rewritten back into memory correctly. If the size of the memory section exceeds a predetermined threshold, then the process of reading and re-writing that section is divided into smaller sub-processes that are distributed in time using a delayed interrupt mechanism. Duration of each memory scrubbing subprocess is kept short enough that the response time of the computer system is not impaired with the housekeeping task of scrubbing RAM memory errors. System management interrupts and firmware may be used to implement the memory-error scrub routine, which makes it independent of and transparent to the various operating systems that may be run on the computer system.

    摘要翻译： 误差校正电路尝试检测并校正计算机系统内随机存取存储器（RAM）内的错误字。 RAM错误被擦除或校正回内存，而不会延迟内存访问周期。 相反，包含可纠正错误的部分或一行RAM的地址被锁存，供以后由中断驱动的固件内存错误擦除例程使用。 该例程读取并重写所指示的存储器部分中的每个单词 - 读取该错误的单词，在读取时在其上进行正确校正，然后将其重写回存储器。 如果存储器部分的大小超过预定阈值，则将该部分的读取和重写的处理分成使用延迟的中断机制在时间上分布的更小的子进程。 每个内存清理子进程的持续时间保持足够短，以免在擦除RAM内存错误的内务任务时计算机系统的响应时间不会受损。 可以使用系统管理中断和固件来实现内存错误擦除例程，这使其独立于可能在计算机系统上运行的各种操作系统的透明度。

    Method and apparatus for hazard detection and distraction avoidance for a vehicle
    8.
    发明授权
    Method and apparatus for hazard detection and distraction avoidance for a vehicle 失效
    用于车辆危害检测和分心避免的方法和装置

    公开(公告)号：US5978737A

    公开(公告)日：1999-11-02

    申请号：US953863

    申请日：1997-10-16

    申请人： Stephen S. Pawlowski ,  Andrew F. Glew ,  George R. Hayek ,  Harshvardhan P. Sharangpani ,  Richard C. Calderwood

    发明人： Stephen S. Pawlowski ,  Andrew F. Glew ,  George R. Hayek ,  Harshvardhan P. Sharangpani ,  Richard C. Calderwood

    IPC分类号： G01S13/93 ,  G01S7/78

    CPC分类号： G01S13/931 ,  G01S2013/9325 ,  G01S2013/9342 ,  G01S2013/9346 ,  G01S2013/9353 ,  G01S2013/9357 ,  G01S2205/002

    摘要： A system for detecting hazardous conditions during operation of a vehicle. In one embodiment, the system includes a plurality of sensors that monitor a plurality of conditions and transmit condition signals each representing a measure of a condition. A plurality of rate determination circuits is coupled to the sensors and continually receives the condition signals, wherein each rate determination circuit calculates rates of change for the condition, including a baseline rate of change, and outputs a potential hazard value representing a deviation of a rate of change from the baseline rate that exceeds a predetermined threshold value. An evaluation circuit receives the potential hazard value, calculates a new potential hazard value using the potential hazard value and a rate of change for at least one associated condition and determines whether an actual hazard exists by comparing the new potential hazard value with a stored value that corresponds to the condition.

    摘要翻译： 一种用于在车辆操作期间检测危险状况的系统。 在一个实施例中，系统包括多个监测多个条件的传感器，并且发送各自表示条件测量的条件信号。 多个速率确定电路耦合到传感器并且连续地接收条件信号，其中每个速率确定电路计算包括基线变化率的条件的变化率，并且输出表示速率偏差的潜在危险值 的基线速率超过预定阈值。 评估电路接收潜在危险值，使用潜在危险值和至少一个相关条件的变化率计算新的潜在危险值，并通过将新的潜在危险值与存储值进行比较来确定是否存在实际危害 对应于条件。

    Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme
    9.
    发明授权
    Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme 失效
    一种用于改善代理在循环仲裁方案下经历的延迟的方法和装置

    公开(公告)号：US5640519A

    公开(公告)日：1997-06-17

    申请号：US528914

    申请日：1995-09-15

    申请人： Brian K. Langendorf ,  James M. Dodd ,  George R. Hayek

    发明人： Brian K. Langendorf ,  James M. Dodd ,  George R. Hayek

    IPC分类号： G06F13/364 ,  G06F13/36 ,  G06F13/362

    CPC分类号： G06F13/364

    摘要： An arbitration circuit which controls arbitration for a resource by a first plurality of agents including a latency sensitive agent. The arbitration circuit comprises a mapping circuit and an arbiter. The mapping circuit is coupled to the first plurality of agents in order to receive a resource request signal from the latency sensitive agent and thereafter produce a plurality of request signals identical to the resource request signal. These request signals are input into at least a first and second I/O ports of the arbiter. The arbiter, which is coupled to the mapping circuit, including a second plurality of I/O ports and a second plurality of control ports each corresponding to one of the I/O ports. The arbiter is configured to arbitrate request signals input into the second plurality of I/O ports including the plurality of request signals, to monitor which I/O port was last activated, and to deactivate a control port associated with the I/O port thereby producing a control signal. This control signal signals the mapping circuit to disable at least one of the plurality of request signals upon detecting that the control signal is associated with the first I/O port or the second I/O port.

    摘要翻译： 仲裁电路，其由包括等待时间敏感代理的第一多个代理控制资源的仲裁。 仲裁电路包括映射电路和仲裁器。 映射电路耦合到第一多个代理，以便从等待时间敏感代理接收资源请求信号，然后产生与资源请求信号相同的多个请求信号。 这些请求信号被输入到仲裁器的至少第一和第二I / O端口中。 耦合到映射电路的仲裁器包括每个对应于一个I / O端口的第二多个I / O端口和第二多个控制端口。 仲裁器被配置为仲裁输入到包括多个请求信号的第二多个I / O端口的请求信号，以监视上一次激活的I / O端口，并且停用与I / O端口相关联的控制端口，从而 产生控制信号。 该控制信号在检测到控制信号与第一I / O端口或第二I / O端口相关联时，通知该映射电路来禁用多个请求信号中的至少一个。

    Performing speculative system memory reads prior to decoding device code
    10.
    发明授权
    Performing speculative system memory reads prior to decoding device code 失效
    在解码设备代码之前执行推测系统存储器读取

    公开(公告)号：US5603010A

    公开(公告)日：1997-02-11

    申请号：US580323

    申请日：1995-12-28

    申请人： James M. Dodd ,  Richard Malinowski ,  Brian K. Langendorf ,  George R. Hayek

    发明人： James M. Dodd ,  Richard Malinowski ,  Brian K. Langendorf ,  George R. Hayek

    IPC分类号： G06F12/04 ,  G06F13/42 ,  G06F13/00

    CPC分类号： G06F13/4239

    摘要： A method of improving computer system performance during memory reads. Prior art computer systems experience a considerable time penalty during microprocessor reads from system memory. This time penalty is mitigated by the method of the present invention, wherein data is speculatively retrieved from system memory upon receipt of a microprocessor read request. A microprocessor initiates a read request which is decoded by a memory controller. Before the decoding has completed, the memory controller speculatively begins to retrieve data from the system memory device. Thus if the decode step determines that the requested data is in system memory, the time required to retrieve the data is decreased.

    摘要翻译： 一种在存储器读取期间提高计算机系统性能的方法。 现有技术的计算机系统在从系统存储器的微处理器读取期间经历相当多的时间损失。 通过本发明的方法减轻了该时间的损失，其中在接收到微处理器读取请求时，从系统存储器中推测性地检索数据。 微处理器启动由存储器控制器解码的读请求。 在解码完成之前，存储器控制器推测开始从系统存储器件中检索数据。 因此，如果解码步骤确定所请求的数据在系统存储器中，则检索数据所需的时间减少。