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    Low load host/PCI bus bridge
    1.
    发明授权
    Low load host/PCI bus bridge 失效
    低负载主机/ PCI总线桥

    公开(公告)号：US5740385A

    公开(公告)日：1998-04-14

    申请号：US358359

    申请日：1994-12-19

    申请人： George R. Hayek ,  Brian K. Langendorf ,  Aniruddha Kundu ,  Kuljit S. Bains ,  Gary A. Solomon

    发明人： George R. Hayek ,  Brian K. Langendorf ,  Aniruddha Kundu ,  Kuljit S. Bains ,  Gary A. Solomon

    IPC分类号： G06F13/40 ,  G06F13/00

    CPC分类号： G06F13/4027

    摘要： A bridge for coupling a host bus to a peripheral component interconnect (PCI) bus. A controller is used to transfer an address from the host bus while a datapath is used to transfer data from the host bus. The address and data is then transferred to the PCI bus over a set of signal lines coupled to the PCI bus such that each signal line transfers at least a portion of the address as well as at least a portion of data.

    摘要翻译： 用于将主机总线耦合到外围组件互连（PCI）总线的桥。 当使用数据路径从主机总线传输数据时，控制器用于从主机总线传输地址。 然后将地址和数据通过耦合到PCI总线的一组信号线传送到PCI总线，使得每个信号线传送地址的至少一部分以及数据的至少一部分。

    Method and apparatus for latching data from a memory resource at a datapath unit
    2.
    发明授权
    Method and apparatus for latching data from a memory resource at a datapath unit 失效
    用于在数据路径单元处从存储器资源锁存数据的方法和装置

    公开(公告)号：US06112284A

    公开(公告)日：2000-08-29

    申请号：US367807

    申请日：1994-12-30

    申请人： George R. Hayek ,  Joe M. Nardone ,  Aniruddha Kundu ,  Kuljit S. Bains

    发明人： George R. Hayek ,  Joe M. Nardone ,  Aniruddha Kundu ,  Kuljit S. Bains

    IPC分类号： G11C7/10 ,  G06F13/16

    CPC分类号： G11C7/1018 ,  G11C7/1024

    摘要： A memory controller having a data strobe that tracks the column access strobe signal in a computer system having Extended Data Out (EDO) DRAMs. The data strobe signal follows, by a predetermined delay, the column access strobe signal, and therefore any skew in the column access strobe signal is inherently included within the data strobe signal. As a result, the data can be latched out, responsive to said data strobe signal, at approximately the center of the valid window.

    摘要翻译： 具有在具有扩展数据输出（EDO）DRAM的计算机系统中跟踪列存取选通信号的数据选通器的存储器控​​制器。 数据选通信号以预定的延迟跟随列存取选通信号，因此列存取选通信号中的任何偏移固有地包括在数据选通信号内。 结果，可以在有效窗口的大约中心处响应于所述数据选通信号来锁存数据。

    High-throughput interconnect allowing bus transactions based on partial access requests
    3.
    发明授权
    High-throughput interconnect allowing bus transactions based on partial access requests 失效
    高吞吐量互连允许基于部分访问请求的总线事务

    公开(公告)号：US5911051A

    公开(公告)日：1999-06-08

    申请号：US721686

    申请日：1996-09-27

    申请人： David G. Carson ,  George R. Hayek ,  Brent S. Baxter ,  Colyn Case ,  Kim A. Meinerth ,  Brian K. Langendorf

    发明人： David G. Carson ,  George R. Hayek ,  Brent S. Baxter ,  Colyn Case ,  Kim A. Meinerth ,  Brian K. Langendorf

    IPC分类号： G06F13/16 ,  G06F13/14

    CPC分类号： G06F13/1631 ,  G06F13/161 ,  G06F13/1615

    摘要： A high throughput memory access interface is provided. The interface includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The interface allows memory access requests to be performed in such a manner that only portions of an access request are required to be transmitted to the target device for certain bus transactions. Each access request includes command bits, address bits, and length bits. In the initiating device, each access request is separated into three segments, which are stored in separate registers in both the initiating device and the target device. Only the segment which contains the lowest order address bits and the length bits is required by the target device to initiate the bus transaction. Thus, if either of the other two segments has not changed since the previous access request, then such segment or segments are not transmitted to the target. If such segment or segments have changed since the previous access request, then they are provided to the target only for purposes of updating state in the target. Access requests may optionally be provided to the target on a separate port from the port used to transmit data in response to access requests.

    摘要翻译： 提供了高吞吐量的存储器访问接口。 该接口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构（如PCI或ISA）可能提供更高数据传输速率的功能。 该接口允许以这样的方式执行存储器访问请求，使得只有访问请求的一部分需要被发送到目标设备以用于某些总线事务。 每个访问请求包括命令位，地址位和长度位。 在发起设备中，每个访问请求被分成三个段，它们存储在起始设备和目标设备中的单独的寄存器中。 目标设备只需要包含最低位地址位和长度位的段来启动总线事务。 因此，如果其他两个段中的任何一个从先前的访问请求起没有改变，则这样的段或段不被发送到目标。 如果这些片段或片段自从先前的访问请求以来已经改变，那么它们被提供给目标，仅用于更新目标中的状态。 访问请求可以可选地在与用于响应于访问请求传输数据的端口的单独端口上提供给目标。

    Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme
    4.
    发明授权
    Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme 失效
    一种用于改善代理在循环仲裁方案下经历的延迟的方法和装置

    公开(公告)号：US5640519A

    公开(公告)日：1997-06-17

    申请号：US528914

    申请日：1995-09-15

    申请人： Brian K. Langendorf ,  James M. Dodd ,  George R. Hayek

    发明人： Brian K. Langendorf ,  James M. Dodd ,  George R. Hayek

    IPC分类号： G06F13/364 ,  G06F13/36 ,  G06F13/362

    CPC分类号： G06F13/364

    摘要： An arbitration circuit which controls arbitration for a resource by a first plurality of agents including a latency sensitive agent. The arbitration circuit comprises a mapping circuit and an arbiter. The mapping circuit is coupled to the first plurality of agents in order to receive a resource request signal from the latency sensitive agent and thereafter produce a plurality of request signals identical to the resource request signal. These request signals are input into at least a first and second I/O ports of the arbiter. The arbiter, which is coupled to the mapping circuit, including a second plurality of I/O ports and a second plurality of control ports each corresponding to one of the I/O ports. The arbiter is configured to arbitrate request signals input into the second plurality of I/O ports including the plurality of request signals, to monitor which I/O port was last activated, and to deactivate a control port associated with the I/O port thereby producing a control signal. This control signal signals the mapping circuit to disable at least one of the plurality of request signals upon detecting that the control signal is associated with the first I/O port or the second I/O port.

    摘要翻译： 仲裁电路，其由包括等待时间敏感代理的第一多个代理控制资源的仲裁。 仲裁电路包括映射电路和仲裁器。 映射电路耦合到第一多个代理，以便从等待时间敏感代理接收资源请求信号，然后产生与资源请求信号相同的多个请求信号。 这些请求信号被输入到仲裁器的至少第一和第二I / O端口中。 耦合到映射电路的仲裁器包括每个对应于一个I / O端口的第二多个I / O端口和第二多个控制端口。 仲裁器被配置为仲裁输入到包括多个请求信号的第二多个I / O端口的请求信号，以监视上一次激活的I / O端口，并且停用与I / O端口相关联的控制端口，从而 产生控制信号。 该控制信号在检测到控制信号与第一I / O端口或第二I / O端口相关联时，通知该映射电路来禁用多个请求信号中的至少一个。

    Performing speculative system memory reads prior to decoding device code
    5.
    发明授权
    Performing speculative system memory reads prior to decoding device code 失效
    在解码设备代码之前执行推测系统存储器读取

    公开(公告)号：US5603010A

    公开(公告)日：1997-02-11

    申请号：US580323

    申请日：1995-12-28

    申请人： James M. Dodd ,  Richard Malinowski ,  Brian K. Langendorf ,  George R. Hayek

    发明人： James M. Dodd ,  Richard Malinowski ,  Brian K. Langendorf ,  George R. Hayek

    IPC分类号： G06F12/04 ,  G06F13/42 ,  G06F13/00

    CPC分类号： G06F13/4239

    摘要： A method of improving computer system performance during memory reads. Prior art computer systems experience a considerable time penalty during microprocessor reads from system memory. This time penalty is mitigated by the method of the present invention, wherein data is speculatively retrieved from system memory upon receipt of a microprocessor read request. A microprocessor initiates a read request which is decoded by a memory controller. Before the decoding has completed, the memory controller speculatively begins to retrieve data from the system memory device. Thus if the decode step determines that the requested data is in system memory, the time required to retrieve the data is decreased.

    摘要翻译： 一种在存储器读取期间提高计算机系统性能的方法。 现有技术的计算机系统在从系统存储器的微处理器读取期间经历相当多的时间损失。 通过本发明的方法减轻了该时间的损失，其中在接收到微处理器读取请求时，从系统存储器中推测性地检索数据。 微处理器启动由存储器控制器解码的读请求。 在解码完成之前，存储器控制器推测开始从系统存储器件中检索数据。 因此，如果解码步骤确定所请求的数据在系统存储器中，则检索数据所需的时间减少。

    System and method for placement of operands in system memory
    6.
    发明授权
    System and method for placement of operands in system memory 失效
    在系统内存中放置操作数的系统和方法

    公开(公告)号：US6097402A

    公开(公告)日：2000-08-01

    申请号：US21192

    申请日：1998-02-10

    申请人： Colyn Case ,  Brian K. Langendorf ,  George R. Hayek ,  Kim A. Meinerth

    发明人： Colyn Case ,  Brian K. Langendorf ,  George R. Hayek ,  Kim A. Meinerth

    IPC分类号： G06F3/14 ,  G06F15/167

    CPC分类号： G06F3/14

    摘要： A method and system for enhancing graphics processing through selected placement of at least one graphics operand in main memory. The system includes a graphics controller in communication with system memory through a dedicated graphics bus such as an Accelerated Graphics Port (AGP) bus. This allows texture maps, alpha blending data and other graphics information to be contained in system memory without degradation of system performance.

    摘要翻译： 一种用于通过在主存储器中选择放置至少一个图形操作数来增强图形处理的方法和系统。 该系统包括通过诸如加速图形端口（AGP）总线的专用图形总线与系统存储器通信的图形控制器。 这允许纹理贴图，alpha混合数据和其他图形信息包含在系统存储器中，而不会降低系统性能。

    High-throughput interconnect having pipelined and non-pipelined bus transaction modes
    7.
    发明授权
    High-throughput interconnect having pipelined and non-pipelined bus transaction modes 失效
    具有流水线和非流水线总线事务模式的高吞吐量互连

    公开(公告)号：US06317803B1

    公开(公告)日：2001-11-13

    申请号：US08721893

    申请日：1996-09-27

    申请人： Norman J. Rasmussen ,  Gary A. Solomon ,  David G. Carson ,  George R. Hayek ,  Brent S. Baxter ,  Colyn Case

    发明人： Norman J. Rasmussen ,  Gary A. Solomon ,  David G. Carson ,  George R. Hayek ,  Brent S. Baxter ,  Colyn Case

    IPC分类号： G06F1300

    CPC分类号： G06F13/1615 ,  G06F13/161 ,  G06F13/1631

    摘要： A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.

    摘要翻译： 提供了高吞吐量的存储器访问端口。 该端口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构（如PCI或ISA）可能提供更高数据传输速率的功能。 该端口允许内存读取和写入请求流水线，以隐藏内存访问延迟的影响。 特别地，端口允许以非流水线模式（例如由PCI提供）或以流水线模式执行总线事务。 在流水线模式中，允许在第一存储器访问请求和其对应的数据传送之间插入一个或多个附加存储器访问请求。 相比之下，在非流水线模式下，不能在第一存储器访问请求和其对应的数据传输之间插入附加存储器访问请求。

    Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge
    8.
    发明授权
    Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge 失效
    仲裁信令机制，以防止死锁保证访问延迟，并保证扩展桥的采集延迟

    公开(公告)号：US5625779A

    公开(公告)日：1997-04-29

    申请号：US366964

    申请日：1994-12-30

    申请人： Gary A. Solomon ,  Peter D. MacWilliams ,  George R. Hayek ,  Nicholas D. Wade ,  Abid Asghar

    发明人： Gary A. Solomon ,  Peter D. MacWilliams ,  George R. Hayek ,  Nicholas D. Wade ,  Abid Asghar

    IPC分类号： G06F13/364 ,  G06F13/40 ,  G06F13/36

    CPC分类号： G06F13/364 ,  G06F13/4031 ,  G06F13/4036

    摘要： An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for storing data to be written into the DRAM. The host bridge also includes an arbiter coupled to receive a request signal from the expansion bridge and any other bus agents coupled to the expansion bridge. Responsive to a request from the expansion bridge, the arbiter empties the CPU posting buffer and the DRAM buffer before asserting an acknowledge signal. A passive release method is provided, which includes signaling a passive release semantic by the expansion bridge during a communication cycle in which the expansion bridge has bus control. The host bridge can grant temporary use of the bus to another bus agent before again granting access to the expansion bridge.

    摘要翻译： 耦合在扩展桥和主桥之间的中间总线的仲裁信令机制，用于管理通过中间总线的通信。 主桥包括用于在CPU和扩展桥之间发布事务的CPU发布缓冲器，以及用于存储要写入到DRAM中的数据的DRAM缓冲器。 主桥还包括耦合以从扩展桥接器和耦合到扩展桥的任何其它总线代理接收请求信号的仲裁器。 响应于扩展桥的请求，仲裁器在确认确认信号之前清空CPU发布缓冲区和DRAM缓冲区。 提供了一种被动释放方法，其包括在扩展桥具有总线控制的通信周期期间通过扩展桥信令发送被动释放语义。 主桥可以在再次允许进入扩建桥之前，暂时使用公交车给另一个总线代理。