公开(公告)号：US08559255B2

公开(公告)日：2013-10-15

申请号：US13569442

申请日：2012-08-08

Applicant: Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

Inventor： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC: G11C7/00

CPC classification number: G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US07957204B1

公开(公告)日：2011-06-07

申请号：US11229667

申请日：2005-09-20

Applicant: Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Sachit Chandra ,  Aaron Lee

Inventor： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Sachit Chandra ,  Aaron Lee

IPC: G11C7/12 ,  G11C8/08 ,  G11C8/12 ,  G11C16/12

CPC classification number: G11C16/12 ,  G11C5/145 ,  G11C8/08

Abstract: A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.

Abstract translation: 非易失性存储器件包括非易失性存储器单元阵列。 当对存储器单元进行编程时，使用包括多个独立电荷泵的电压源。 独立电荷泵将编程电压提供给存储器单元阵列中的不同位线。 使用多个电荷泵倾向于降低输出电压波动，从而降低功率损耗。

公开(公告)号：US07453724B2

公开(公告)日：2008-11-18

申请号：US11931992

申请日：2007-10-31

Applicant: Aaron Lee ,  Hounien Chen ,  Sachit Chandra ,  Nancy Leong ,  Guowei Wang

Inventor： Aaron Lee ,  Hounien Chen ,  Sachit Chandra ,  Nancy Leong ,  Guowei Wang

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C16/0475 ,  G11C16/3454 ,  G11C16/3459

Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器件进行编程的方法，其中每个存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收标识阵列中的多个存储单元的编程窗口。 在编程窗口中从多个存储器单元识别要编程的第一组存储器单元。 第一组存储器单元被编程，并且验证第一组存储器单元的编程状态。

公开(公告)号：US20120294103A1

公开(公告)日：2012-11-22

申请号：US13569442

申请日：2012-08-08

Applicant: Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

Inventor： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC: G11C7/12

CPC classification number: G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US07679967B2

公开(公告)日：2010-03-16

申请号：US11963508

申请日：2007-12-21

Applicant: Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

Inventor： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC: G11C16/06

CPC classification number: G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US20090273998A1

公开(公告)日：2009-11-05

申请号：US12114966

申请日：2008-05-05

Applicant: Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

Inventor： Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

IPC: G11C7/06

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C7/08 ,  G11C2207/063

Abstract: A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.

Abstract translation: 存储器件包括用于感测位单元的状态的读出放大器。 读出放大器包括通过开关连接的两个输入端。 一个输入端子连接到一个节点，由此通过该节点的电流表示由位单元和参考电流所画出的电流差。 在第一阶段期间，读出放大器的输入端之间的开关闭合，使得两个输入端施加公共电压。 在第二阶段期间，开关被打开，并且感测放大器基于通过节点的电流来感测存储在位单元的信息的状态。 通过使用开关来连接和断开两相中的读出放大器的输入，可以确定存储在位单元中的信息的状态的精度和速度。

公开(公告)号：US07443732B2

公开(公告)日：2008-10-28

申请号：US11229527

申请日：2005-09-20

Applicant: Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael A. VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Quang Le

Inventor： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael A. VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Quang Le

IPC: G11C11/34

CPC classification number: G11C5/147 ,  G11C16/12

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。 预定数量的位同时被编程到阵列中的对应存储器单元。 同时验证阵列中预定位数的编程状态。

公开(公告)号：US20080130371A1

公开(公告)日：2008-06-05

申请号：US11950811

申请日：2007-12-05

Applicant: Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

Inventor： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC: G11C16/12 ,  G11C16/28

CPC classification number: G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US20080049516A1

公开(公告)日：2008-02-28

申请号：US11931992

申请日：2007-10-31

Applicant: Aaron LEE ,  Hounien CHEN ,  Sachit CHANDRA ,  Nancy LEONG ,  Guowei WANG

Inventor： Aaron LEE ,  Hounien CHEN ,  Sachit CHANDRA ,  Nancy LEONG ,  Guowei WANG

IPC: G11C11/34

CPC classification number: G11C16/0475 ,  G11C16/3454 ,  G11C16/3459

Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.

Abstract translation: 提供了一种用于对包括存储器单元阵列的非易失性存储器件进行编程的方法，其中每个存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收标识阵列中的多个存储单元的编程窗口。 在编程窗口中从多个存储器单元识别要编程的第一组存储器单元。 第一组存储器单元被编程，并且验证第一组存储器单元的编程状态。

公开(公告)号：US06542435B1

公开(公告)日：2003-04-01

申请号：US09531871

申请日：2000-03-21

Applicant: Guowei Wang

Inventor： Guowei Wang

IPC: G11C800

CPC classification number: G11C8/18

Abstract: A method and apparatus ensure equal address transition detection (ATD) pulse width for all address and chip enable transitions. Address buffer signals from one end of an integrated circuit are combined to form a first combined signal. Address buffer signals and a chip enable signal from a second end of the integrated circuit are combined to form a second combined signal. The two combined signals are logically combined to form a first edge of an ATD pulse. A feedback signal controls the second edge of the ATD pulse for all input signal transitions.

Abstract translation: 一种方法和装置确保所有地址和芯片使能转换的等同地址转换检测（ATD）脉冲宽度。 来自集成电路一端的地址缓冲器信号被组合以形成第一组合信号。 来自集成电路的第二端的地址缓冲器信号和芯片使能信号被组合以形成第二组合信号。 两个组合信号被逻辑地组合以形成ATD脉冲的第一边缘。 反馈信号控制所有输入信号转换的ATD脉冲的第二个边沿。