公开(公告)号：US20090020845A1

公开(公告)日：2009-01-22

申请号：US12106671

申请日：2008-04-21

Applicant: Dong-suk Shin ,  Moon-han Park ,  Joo-won Lee ,  Jae-yoon Yoo ,  Tae-gyun Kim

Inventor： Dong-suk Shin ,  Moon-han Park ,  Joo-won Lee ,  Jae-yoon Yoo ,  Tae-gyun Kim

IPC: H01L21/762 ,  H01L23/00

CPC classification number: H01L21/3105 ,  H01L21/31155 ,  H01L21/76232

Abstract: A semiconductor device includes a substrate having a trench, a sidewall liner that covers inner walls of the trench, a doped oxide film liner on the sidewall liner in the trench, and a gap-fill insulating film that buries the trench on the doped oxide film liner. In order to form the doped oxide film liner, an oxide film liner is doped with a dopant under a plasma atmosphere. Related methods are also disclosed.

Abstract translation: 半导体器件包括具有沟槽的衬底，覆盖沟槽的内壁的侧壁衬套，沟槽中的侧壁衬里上的掺杂氧化膜衬垫，以及将掺杂氧化物膜上的沟槽埋入的间隙填充绝缘膜 衬垫。 为了形成掺杂的氧化物膜衬垫，在等离子体气氛下，掺杂有氧化物膜衬垫。 还公开了相关方法。

公开(公告)号：US20060183296A1

公开(公告)日：2006-08-17

申请号：US11398536

申请日：2006-04-06

Applicant: Jae-yoon Yoo ,  Moon-han Park ,  Dong-ho Ahn ,  Sug-hun Hong ,  Kyung-won Park ,  Jeong-soo Lee

Inventor： Jae-yoon Yoo ,  Moon-han Park ,  Dong-ho Ahn ,  Sug-hun Hong ,  Kyung-won Park ,  Jeong-soo Lee

IPC: H01L21/76

CPC classification number: H01L21/76232

Abstract: An isolation method for a semiconductor device where an insulating mask layer is formed on desired regions of a semiconductor substrate. A trench is formed to a desired depth in the semiconductor substrate using the insulating mask layer as a mask. An oxide layer is formed on the insulating mask layer and on the sidewall of the trench. A trench liner layer is formed on the oxide layer. An insulating filler layer is formed in the trench in the semiconductor substrate, on which the trench liner layer is formed, so as to fill the trench. The insulating mask layer is removed. According to the isolation method for a semiconductor device, it is possible to reduce dents from occurring along the edge of the trench, reduce a bird's beak type oxide layer from occurring at an interface between the insulating mask layers, decrease the leakage current, or improve the electrical characteristics, such as threshold voltage.

公开(公告)号：US07033895B2

公开(公告)日：2006-04-25

申请号：US10823420

申请日：2004-04-13

Applicant: Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

Inventor： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

IPC: H01L21/336

CPC classification number: H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

Abstract: In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

Abstract translation: 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

公开(公告)号：US20050170620A1

公开(公告)日：2005-08-04

申请号：US11045060

申请日：2005-01-31

Applicant: Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee ,  Hyun-Suk Kim ,  Moon-Han Park

Inventor： Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee ,  Hyun-Suk Kim ,  Moon-Han Park

IPC: H01L21/00 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66537 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention discloses a transistor for a semiconductor device capable of preventing the generation of a depletion capacitance in a gate pattern due to the diffusion of impurity ions. The present invention also discloses a method of fabricating the transistor.

Abstract translation: 本发明公开了一种用于半导体器件的晶体管，其能够防止由于杂质离子的扩散而产生栅极图案中的耗尽电容。 本发明还公开了一种制造晶体管的方法。

公开(公告)号：US06835621B2

公开(公告)日：2004-12-28

申请号：US10455676

申请日：2003-06-05

Applicant: Jae-yoon Yoo ,  Moon-han Park ,  Dae-jin Kwon

Inventor： Jae-yoon Yoo ,  Moon-han Park ,  Dae-jin Kwon

IPC: H01L218247

CPC classification number: H01L27/11568 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02326 ,  H01L21/28282 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/32105 ,  H01L27/115 ,  H01L29/66833

Abstract: In a method of fabricating a non-volatile memory device with a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a silicon nitride layer, which is a charge trapping layer, and a polysilicon layer, which is a control gate electrode, are electrically isolated from one another in the resulting structure. According to the method, a silicon oxide layer as a tunneling layer and a silicon nitride layer pattern as a charge trapping layer are formed on a semiconductor substrate; an oxidation process is performed to form a silicon nitride oxide layer, as a blocking layer, at top and sides of the silicon nitride layer pattern and to form a gate insulating layer at an exposed portion of the semiconductor substrate; and a control gate electrode is formed on the silicon nitride oxide layer and the gate insulating layer.

Abstract translation: 在制造具有氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）结构的非易失性存储器件的方法中，作为电荷俘获层的氮化硅层和作为控制栅电极的多晶硅层 在所得结构中彼此电隔离。 根据该方法，在半导体衬底上形成作为隧穿层的氧化硅层和作为电荷俘获层的氮化硅层图案; 进行氧化处理以在氮化硅层图案的顶部和侧面形成氮化硅氧化物层作为阻挡层，并在半导体衬底的暴露部分形成栅极绝缘层; 并且在氮氧化硅层和栅极绝缘层上形成控制栅电极。

公开(公告)号：US06383877B1

公开(公告)日：2002-05-07

申请号：US09573268

申请日：2000-05-18

Applicant: Dong-ho Ahn ,  Ja-hum Ku ,  Chul-sung Kim ,  Jae-yoon Yoo ,  Sug-hun Hong ,  Chul-joon Choi

Inventor： Dong-ho Ahn ,  Ja-hum Ku ,  Chul-sung Kim ,  Jae-yoon Yoo ,  Sug-hun Hong ,  Chul-joon Choi

IPC: H01L21425

CPC classification number: H01L29/66598 ,  H01L21/28518 ,  H01L21/76232 ,  H01L21/823481 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66636

Abstract: A method of forming a T-shaped isolation layer, a method of forming an elevated salicide source/drain region using the same, and a semiconductor device having the T-shaped isolation layer are provided. In the method of forming the T-shaped isolation layer, an isolation layer having a narrow trench region in the lower portion thereof and a wide trench region in the upper portion thereof is formed on a semiconductor substrate. Also, in the method of forming the elevated salicide source/drain region, the method of forming the T-shaped isolation layer is used. In particular, conductive impurities can also be implanted into the lower portion of the wide trench region which constitutes the head of the T-shaped isolation layer and is extended to both sides from the upper end of the narrow trench region by controlling the depth of the wide trench region in an ion implantation step for forming the source/drain region.

Abstract translation: 提供形成T形隔离层的方法，使用该方法形成提高的自对准硅化物源极/漏极区域的方法以及具有T形隔离层的半导体器件。 在形成T形隔离层的方法中，在半导体衬底上形成在其下部具有窄沟槽区和其上部宽沟槽区的隔离层。 此外，在形成升高的自对准硅化物源极/漏极区域的方法中，使用形成T形隔离层的方法。 特别地，也可以将导电杂质注入构成T形隔离层的头部的宽沟槽区域的下部，并且通过控制该窄沟槽区域的深度而从窄沟槽区域的上端延伸到两侧 在用于形成源极/漏极区域的离子注入步骤中形成宽沟槽区域。

公开(公告)号：US07101776B2

公开(公告)日：2006-09-05

申请号：US10806301

申请日：2004-03-22

Applicant: Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

Inventor： Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

IPC: H01L21/44 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/66545

Abstract: There is provided a method of fabricating a MOS transistor using a total gate silicidation process. The method includes forming an insulated gate pattern on a semiconductor substrate. The insulated gate pattern includes a silicon pattern and a sacrificial layer pattern, which are sequentially stacked. Spacers covering sidewalls of the gate pattern are formed, and source/drain regions are formed by injecting impurity ions into the semiconductor substrate using the spacers and the gate pattern as ion injection masks. The silicon pattern is exposed by removing the sacrificial layer pattern on the semiconductor substrate having the source/drain regions. The exposed silicon pattern is fully converted into a gate silicide layer, and concurrently a source/drain silicide layer is selectively formed on the surface of the source/drain regions.

Abstract translation: 提供了使用总栅极硅化工艺制造MOS晶体管的方法。 该方法包括在半导体衬底上形成绝缘栅极图案。 绝缘栅图案包括依次层叠的硅图案和牺牲层图案。 形成覆盖栅极图案的侧壁的间隔物，并且通过使用间隔物和栅极图案作为离子注入掩模将杂质离子注入到半导体衬底中来形成源极/漏极区域。 通过去除具有源极/漏极区域的半导体衬底上的牺牲层图案来暴露硅图案。 暴露的硅图案完全转换为栅极硅化物层，并且同时在源极/漏极区域的表面上选择性地形成源极/漏极硅化物层。

公开(公告)号：US20050274981A1

公开(公告)日：2005-12-15

申请号：US11194529

申请日：2005-08-02

Applicant: Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

Inventor： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

IPC: H01L21/20 ,  H01L21/8238 ,  H01L31/072 ,  H01L31/117

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251

Abstract: A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

Abstract translation: 半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。 异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。 在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。 此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。 中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。 因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。

公开(公告)号：US20050009265A1

公开(公告)日：2005-01-13

申请号：US10806301

申请日：2004-03-22

Applicant: Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

Inventor： Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/84

CPC classification number: H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/66545

Abstract: There is provided a method of fabricating a MOS transistor using a total gate silicidation process. The method includes forming an insulated gate pattern on a semiconductor substrate. The insulated gate pattern includes a silicon pattern and a sacrificial layer pattern, which are sequentially stacked. Spacers covering sidewalls of the gate pattern are formed, and source/drain regions are formed by injecting impurity ions into the semiconductor substrate using the spacers and the gate pattern as ion injection masks. The silicon pattern is exposed by removing the sacrificial layer pattern on the semiconductor substrate having the source/drain regions. The exposed silicon pattern is fully converted into a gate silicide layer, and concurrently a source/drain silicide layer is selectively formed on the surface of the source/drain regions.

Abstract translation: 提供了使用总栅极硅化工艺制造MOS晶体管的方法。 该方法包括在半导体衬底上形成绝缘栅极图案。 绝缘栅图案包括依次层叠的硅图案和牺牲层图案。 形成覆盖栅极图案的侧壁的间隔物，并且通过使用间隔物和栅极图案作为离子注入掩模将杂质离子注入到半导体衬底中来形成源极/漏极区域。 通过去除具有源极/漏极区域的半导体衬底上的牺牲层图案来暴露硅图案。 暴露的硅图案完全转换为栅极硅化物层，并且同时在源极/漏极区域的表面上选择性地形成源极/漏极硅化物层。

公开(公告)号：US07723193B2

公开(公告)日：2010-05-25

申请号：US12149329

申请日：2008-04-30

Applicant: Hwa-Sung Rhee ,  Hyun-Suk Kim ,  Ueno Tetsuji ,  Jae-Yoon Yoo ,  Seung-Hwan Lee ,  Ho Lee ,  Moon-han Park

Inventor： Hwa-Sung Rhee ,  Hyun-Suk Kim ,  Ueno Tetsuji ,  Jae-Yoon Yoo ,  Seung-Hwan Lee ,  Ho Lee ,  Moon-han Park

IPC: H01L21/336

CPC classification number: H01L29/7853 ,  H01L29/66795

Abstract: An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.

Abstract translation: 至少五面通道类型的FinFET晶体管可以包括：基极; 形成在所述基座上的半导体本体，所述主体被布置成较长的尺寸，以使源极/漏极区域夹持沟道区域，至少所述沟道横截面与所述长尺寸的横截面具有至少五个平面 基础; 主体通道区上的栅极绝缘体; 以及形成在栅极绝缘体上的栅电极。