摘要:
A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.
摘要:
A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
摘要:
A method of sputtering a Ta layer comprised of alpha phase Ta on a Cu layer. An embodiment includes a Ta sputter deposition on a Cu surface at a substrate temperature less than 200° C. Another embodiment has a pre-cooling step at a temperature less than 100° C. prior to Ta layer sputter deposition. In another non-limiting example embodiment, a pre-clean step comprising an inert gas sputter is performed prior to the tantalum sputter. Another non-limiting example embodiment provides a semiconductor structure comprising: a semiconductor structure; a copper layer over the semiconductor structure; a tantalum layer on the copper layer; the tantalum layer comprised alpha phase Ta; a metal layer on the tantalum layer.
摘要:
An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.
摘要:
A method of forming a dual damascene structure with improved performance is described. A first etch stop layer comprised of oxygen doped SiC is deposited on a SiC barrier layer to form a composite barrier/etch stop layer on a substrate. The remainder of the damascene stack is formed by sequentially depositing a first dielectric layer, a second oxygen doped SiC etch stop layer, and a second dielectric layer. A via and overlying trench are formed and filled with a diffusion barrier layer and a metal layer. The oxygen doped SiC layers have a lower dielectric constant than SiC or SiCN and a higher breakdown field than SiC. The etch selectivity of a C4F8/Ar etch for a SiCOH layer relative to the oxygen doped SiC layer is at least 6:1 because of a lower oxygen content in the oxygen doped SiC layer.
摘要翻译:描述了一种形成具有改进性能的双镶嵌结构的方法。 由氧掺杂的SiC构成的第一蚀刻停止层沉积在SiC阻挡层上,以在衬底上形成复合势垒/蚀刻停止层。 镶嵌层的剩余部分通过依次沉积第一介电层,第二氧掺杂的SiC蚀刻停止层和第二介电层而形成。 形成通孔和上覆沟槽并填充有扩散阻挡层和金属层。 氧掺杂的SiC层具有比SiC或SiCN更低的介电常数和比SiC更高的击穿场。 对于SiCOH层,相对于氧掺杂的SiC层,C 4 Si 8 N / Ar蚀刻的蚀刻选择性至少为6:1,因为氧含量低 氧掺杂的SiC层。
摘要:
A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
摘要:
A method of forming a dual damascene structure with improved performance is described. A first etch stop layer comprised of oxygen doped SiC is deposited on a SiC barrier layer to form a composite barrier/etch stop layer on a substrate. The remainder of the damascene stack is formed by sequentially depositing a first dielectric layer, a second oxygen doped SiC etch stop layer, and a second dielectric layer. A via and overlying trench are formed and filled with a diffusion barrier layer and a metal layer. The oxygen doped SiC layers have a lower dielectric constant than SiC or SIGN and a higher breakdown field than SiC. The etch selectivity of a C4F8/Ar etch for a SiCOH layer relative to the oxygen doped SiC layer is at least 6:1 because of a lower oxygen content in the oxygen doped SiC layer.
摘要翻译:描述了一种形成具有改进性能的双镶嵌结构的方法。 由氧掺杂的SiC构成的第一蚀刻停止层沉积在SiC阻挡层上,以在衬底上形成复合势垒/蚀刻停止层。 镶嵌层的剩余部分通过依次沉积第一介电层,第二氧掺杂的SiC蚀刻停止层和第二介电层而形成。 形成通孔和上覆沟槽并填充有扩散阻挡层和金属层。 氧掺杂的SiC层具有比SiC或SIGN更低的介电常数和比SiC更高的击穿场。 对于SiCOH层,相对于氧掺杂的SiC层,C 4 Si 8 N / Ar蚀刻的蚀刻选择性为至少6:1,因为氧含量低 氧掺杂的SiC层。
摘要:
A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
摘要:
A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal track thereover are provided. A metal bump is formed over the exposed metal terminating pad. A photosensitive resin plug is formed over the metal bump. The metal bump of the semiconductor chip is aligned with the corresponding metal track on the separate substrate. The photosensitive resin plug over the metal bump is mated with the corresponding the metal track. The photosensitive resin plug is exposed to UV light to cure the photosensitive resin plug, permanently attaching the metal bump of the semiconductor chip to the corresponding metal track of the separate substrate.
摘要:
A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.