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    Semiconductor device of an LDD structure having a floating gate
    2.
    发明授权
    Semiconductor device of an LDD structure having a floating gate 失效
    具有浮动栅极的LDD结构的半导体器件

    公开(公告)号：US5194924A

    公开(公告)日：1993-03-16

    申请号：US781592

    申请日：1991-10-23

    申请人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

    发明人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

    IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/105

    CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546

    摘要： Disclosed is a semiconductor integrated circuit device which includes first field effect transistors with an LDD structure having a floating gate in memory cells and second field effect transistors with an LDD structure as elements other than memory cells, and which is used as an EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.

    摘要翻译： 公开了一种半导体集成电路器件，其包括具有在存储器单元中具有浮动栅极的LDD结构的第一场效应晶体管和具有作为除了存储器单元之外的元素的LDD结构的第二场效应晶体管，并且被用作EPROM。 作为其源极或漏极区域的一部分的第一场效应晶体管的浅的低杂质浓度区域具有比作为其源极或漏极区域的一部分的第二场效应晶体管的浅的，低杂质浓度区域的杂质浓度更高的杂质浓度 。

    Semiconductor memory
    4.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US4788665A

    公开(公告)日：1988-11-29

    申请号：US75986

    申请日：1987-07-21

    申请人： Minoru Fukuda ,  Hideaki Takahashi ,  June Sugiura ,  Fumio Tsuchiya ,  Toshimasa Kihara

    发明人： Minoru Fukuda ,  Hideaki Takahashi ,  June Sugiura ,  Fumio Tsuchiya ,  Toshimasa Kihara

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/10 ,  G11C8/00

    CPC分类号： G11C16/10 ,  G11C2216/14

    摘要： An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converted parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of the parallel signal action.

    摘要翻译： 电可编程只读存储器配备有用于顺序地引入通过外部端子馈送的串联信号的锁存电路。 转换器包括顺序操作的开关元件和锁存电路，以将串联信号转换为并行信号。 这样转换的并行信号通过地址译码器操作的选择开关元件同时写入存储器阵列。 根据这种方法，即使当并行信号动作的结果是一个写入操作相对较长时，也可以高速地进行对存储器阵列的写入操作。

    Method of making semiconductor device with memory cells and peripheral transistors
    7.
    发明授权
    Method of making semiconductor device with memory cells and peripheral transistors 失效
    制造具有存储单元和外围晶体管的半导体器件的方法

    公开(公告)号：US5352620A

    公开(公告)日：1994-10-04

    申请号：US71343

    申请日：1993-06-02

    申请人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

    发明人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

    IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/105 ,  H01L21/70

    CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546

    摘要： Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.

    摘要翻译： 公开了一种半导体集成电路器件，其包括作为存储单元的浮动栅极的LDD结构的第一场效应晶体管和LDD结构的第二场效应晶体管作为除了存储单元之外的元件，并且被用作EPROM。 作为其源极或漏极区域的一部分的第一场效应晶体管的浅的低杂质浓度区域具有比作为其源极或漏极区域的一部分的第二场效应晶体管的浅的，低杂质浓度区域的杂质浓度更高的杂质浓度 。

    Semiconductor device of an LDD structure having a floating gate
    9.
    发明授权
    Semiconductor device of an LDD structure having a floating gate 失效
    具有浮动栅极的LDD结构的半导体器件

    公开(公告)号：US4663645A

    公开(公告)日：1987-05-05

    申请号：US736770

    申请日：1985-05-22

    申请人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

    发明人： Kazuhiro Komori ,  Kenichi Kuroda ,  June Sugiura

    IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/78 ,  H01L29/68

    CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546 ,  Y10S257/90

    摘要： A semiconductor integrated circuit device is provided which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells. A shallow, low impurity concentration region of the first field effect transistor which is a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor which is a part of its source or drain region. The device is particularly useful in an EPROM arrangement.

    摘要翻译： 提供一种半导体集成电路器件，其包括作为存储单元的浮动栅极的LDD结构的第一场效应晶体管和作为存储单元之外的元件的LDD结构的第二场效应晶体管。 作为其源极或漏极区域的一部分的第一场效应晶体管的浅的低杂质浓度区域具有比作为其源极的一部分的第二场效应晶体管的浅的低杂质浓度区域更高的杂质浓度，或 漏区。 该装置在EPROM装置中特别有用。