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公开(公告)号：US20110234472A1
公开(公告)日：2011-09-29
申请号：US12748709
申请日：2010-03-29
CPC分类号： H01L23/66 , H01L2223/6627 , H01L2223/6677 , H01L2924/0002 , H01L2924/09701 , H01L2924/1903 , H01P5/107 , H01Q1/2283 , H01Q1/52 , H01Q9/0407 , H01Q13/06 , H01L2924/00
摘要： Some embodiments herein relate to a transmitter. The transmitter includes an integrated circuit (IC) package including a first antenna configured to radiate a first electromagnetic signal therefrom. A printed circuit board (PCB) substrate includes a waveguide configured to receive the first electromagnetic signal and to generate a waveguide signal based thereon. A second antenna can be electrically coupled to the waveguide and can radiate a second electromagnetic signal that corresponds to the waveguide signal. Other devices and methods are also disclosed.
摘要翻译： 本文中的一些实施例涉及发射机。 发射机包括集成电路（IC）封装，其包括被配置为从其辐射第一电磁信号的第一天线。 印刷电路板（PCB）基板包括配置为接收第一电磁信号并基于其产生波导信号的波导。 第二天线可以电耦合到波导并且可以辐射对应于波导信号的第二电磁信号。 还公开了其它装置和方法。
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2.发明授权Analog-to-digital converter, receiver arrangement, filter arrangement and signal processing method 失效模数转换器，接收器布置，滤波器布置和信号处理方法公开(公告)号：US07495595B2
公开(公告)日：2009-02-24
申请号：US11742307
申请日：2007-04-30
IPC分类号： H03M1/12
CPC分类号： H03H19/004 , H03M3/344 , H03M3/424
摘要： A filter arrangement comprises a switching element coupled to a filter input, wherein the switching element is controllable by a reference clock signal. The filter arrangement further comprises an input storage element, an output storage element, and a first and a second auxiliary storage element. The first and the second auxiliary storage element can each be connected in parallel to the input storage element or to the output storage element depending on a switching signal. The output storage element is coupled to a filter output. The filter arrangement can be used as a loop filter in an analog-to-digital converter, wherein the output signal of the filter arrangement is quantized to provide an output word. Respective feedback signals can be generated from the output word and be provided to the storage elements.
摘要翻译： 滤波器装置包括耦合到滤波器输入的开关元件，其中开关元件由参考时钟信号控制。 滤波器装置还包括输入存储元件，输出存储元件以及第一和第二辅助存储元件。 第一和第二辅助存储元件可以各自根据切换信号并联连接到输入存储元件或输出存储元件。 输出存储元件耦合到滤波器输出。 滤波器装置可以用作模数转换器中的环路滤波器，其中滤波器装置的输出信号被量化以提供输出字。 可以从输出字生成各个反馈信号，并将其提供给存储元件。
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3.再颁专利Phase locked loop, transceiver device and method for generating an oscillator signal 有权锁相环，收发器装置和用于产生振荡器信号的方法公开(公告)号：USRE44879E1
公开(公告)日：2014-05-06
申请号：US13440521
申请日：2012-04-05
IPC分类号： H03L7/00
摘要： A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.
摘要翻译： 锁相环具有受控振荡器，用于根据控制信号输出振荡器信号。 比较器从参考频率信号和从振荡器信号导出的反馈信号之间的比较产生比较结果。 锁相环还具有用于对比较结果进行滤波和从比较结果导出控制信号的滤波器块，其中滤波器块具有环路滤波器和用于至少一个第一干扰频率的频率选择衰减的抑制滤波器 在比较结果中。
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公开(公告)号：US08278749B2
公开(公告)日：2012-10-02
申请号：US12645969
申请日：2009-12-23
申请人： Rudolf Lachner , Linus Maurer , Maciej Wojnowski
发明人： Rudolf Lachner , Linus Maurer , Maciej Wojnowski
IPC分类号： H01L23/538 , H01L21/50
CPC分类号： H01L23/66 , H01L23/3128 , H01L23/3135 , H01L24/12 , H01L24/19 , H01L2223/6611 , H01L2223/6655 , H01L2223/6677 , H01L2223/6683 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/32225 , H01L2224/48247 , H01L2224/73204 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1423 , H01L2924/181 , H01L2924/1815 , H01L2924/18162 , H01L2924/19107 , H01L2924/3011 , H01L2924/351 , H01Q1/2283 , H01Q9/0407 , H01Q9/045 , H01Q9/0457 , H01L2924/00
摘要： A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process.
摘要翻译： 半导体模块包括一个晶片级封装中的部件。 该模块包括嵌入在封装模塑料中的集成电路（IC）芯片。 该封装包括耦合到界面层的成型复合封装层，用于将天线结构和接合互连结构集成到IC芯片。 接合互连结构包括三维互连。 天线结构和接合互连结构在相同的晶片制造过程中耦合到IC芯片并且集成在界面层内。
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公开(公告)号：US20100193935A1
公开(公告)日：2010-08-05
申请号：US12645969
申请日：2009-12-23
申请人： Rudolf Lachner , Linus Maurer , Maciej Wojnowski
发明人： Rudolf Lachner , Linus Maurer , Maciej Wojnowski
IPC分类号： H01L23/538 , H01L21/50
CPC分类号： H01L23/66 , H01L23/3128 , H01L23/3135 , H01L24/12 , H01L24/19 , H01L2223/6611 , H01L2223/6655 , H01L2223/6677 , H01L2223/6683 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/32225 , H01L2224/48247 , H01L2224/73204 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1423 , H01L2924/181 , H01L2924/1815 , H01L2924/18162 , H01L2924/19107 , H01L2924/3011 , H01L2924/351 , H01Q1/2283 , H01Q9/0407 , H01Q9/045 , H01Q9/0457 , H01L2924/00
摘要： A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process.
摘要翻译： 半导体模块包括一个晶片级封装中的部件。 该模块包括嵌入在封装模塑料中的集成电路（IC）芯片。 该封装包括耦合到界面层的成型复合封装层，用于将天线结构和接合互连结构集成到IC芯片。 接合互连结构包括三维互连。 天线结构和接合互连结构在相同的晶片制造过程中耦合到IC芯片并且集成在界面层内。
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6.发明授权Phase locked loop, transceiver device and method for generating an oscillator signal 有权锁相环，收发器装置和用于产生振荡器信号的方法公开(公告)号：US07692498B2
公开(公告)日：2010-04-06
申请号：US11925379
申请日：2007-10-26
IPC分类号： H03L7/00
摘要： A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.
摘要翻译： 锁相环具有受控振荡器，用于根据控制信号输出振荡器信号。 比较器从参考频率信号和从振荡器信号导出的反馈信号之间的比较产生比较结果。 锁相环还具有用于对比较结果进行滤波和从比较结果导出控制信号的滤波器块，其中滤波器块具有环路滤波器和用于至少一个第一干扰频率的频率选择衰减的抑制滤波器 在比较结果中。
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7.发明申请ANALOG-TO-DIGITAL CONVERTER, RECEIVER ARRANGEMENT, FILTER ARRANGEMENT AND SIGNAL PROCESSING METHOD 失效模拟数字转换器，接收器布置，滤波器布置和信号处理方法公开(公告)号：US20080266161A1
公开(公告)日：2008-10-30
申请号：US11742307
申请日：2007-04-30
CPC分类号： H03H19/004 , H03M3/344 , H03M3/424
摘要： A filter arrangement comprises a switching element coupled to a filter input, wherein the switching element is controllable by a reference clock signal. The filter arrangement further comprises an input storage element, an output storage element, and a first and a second auxiliary storage element. The first and the second auxiliary storage element can each be connected in parallel to the input storage element or to the output storage element depending on a switching signal. The output storage element is coupled to a filter output. The filter arrangement can be used as a loop filter in an analog-to-digital converter, wherein the output signal of the filter arrangement is quantized to provide an output word. Respective feedback signals can be generated from the output word and be provided to the storage elements.
摘要翻译： 滤波器装置包括耦合到滤波器输入的开关元件，其中开关元件由参考时钟信号控制。 滤波器装置还包括输入存储元件，输出存储元件以及第一和第二辅助存储元件。 第一和第二辅助存储元件可以各自根据切换信号并联连接到输入存储元件或输出存储元件。 输出存储元件耦合到滤波器输出。 滤波器装置可以用作模数转换器中的环路滤波器，其中滤波器装置的输出信号被量化以提供输出字。 可以从输出字生成各个反馈信号，并将其提供给存储元件。
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公开(公告)号：US07420485B2
公开(公告)日：2008-09-02
申请号：US11726844
申请日：2007-03-23
IPC分类号： H03M3/00
CPC分类号： H03M7/3015
摘要： A sigma-delta modulator is supplied with a data word and includes a first and at least one further modulation stage, each having at least two adders. The adders in the first modulation stage process a low-significance component and a delayed more significant component of the data word and provide a result word and a carry at their respective outputs. The adders in the at least one further modulation stage process a low-significance component and a more significant component of the result word and provide a further result word and a carry at their respective outputs. The low-significance component and the more significant component of the result word are provided to the further modulation stages with an unvarying delay. A bit stream is derived from a carry from final instances of the at least two adders in the first modulation stage and in the further modulation stage respectively.
摘要翻译： Σ-Δ调制器被提供有数据字，并且包括第一和至少一个另外的调制级，每个具有至少两个加法器。 第一调制级中的加法器处理数据字的低有效分量和延迟更高有效分量，并在其各自的输出端提供结果字和进位。 所述至少一个另外的调制级中的加法器处理结果字的低有效分量和更重要的分量，并在其各自的输出端提供另外的结果字和进位。 结果字的低有效分量和更重要的分量被提供给具有不变延迟的进一步的调制阶段。 从第一调制阶段和另外的调制阶段的至少两个加法器的最终实例的进位分别导出比特流。
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9.发明申请ARRANGEMENT AND METHOD FOR DETERMINING A GRADIENT FACTOR FOR A DIGITALLY CONTROLLED OSCILLATOR, AND PHASE LOCKED LOOP 有权用于确定数字控制振荡器的梯度因子的装配和方法以及相位锁定环公开(公告)号：US20080042753A1
公开(公告)日：2008-02-21
申请号：US11840408
申请日：2007-08-17
申请人： Thomas Bauernfeind , Linus Maurer
发明人： Thomas Bauernfeind , Linus Maurer
CPC分类号： H03C3/0925 , H03C3/0941 , H03C3/095 , H03L7/093 , H03L7/095 , H03L7/0991 , H03L7/187 , H03L7/1976
摘要： An arrangement for determining a gradient factor for a digitally controlled oscillator has a data alignment device and an identification device. The data alignment device can be supplied a modulation signal, a phase error signal and an oscillator control word. The data alignment device is configured to output a modulation setting word based on the modulation signal, output a time interval magnitude based on the phase error signal and a reference interval, and output an oscillator modulation word based on the oscillator control word. The identification device is configured to adapt and output the gradient factor based on the modulation setting word, the time interval magnitude and the oscillator modulation word.
摘要翻译： 用于确定数字控制振荡器的梯度因子的装置具有数据对准装置和识别装置。 可以向数据对准装置提供调制信号，相位误差信号和振荡器控制字。 数据对准装置被配置为基于调制信号输出调制设置字，基于相位误差信号和参考间隔输出时间间隔幅度，并且基于振荡器控制字输出振荡器调制字。 识别装置被配置为基于调制设置字，时间间隔幅度和振荡器调制字来适应和输出梯度因子。
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公开(公告)号：US20120187511A1
公开(公告)日：2012-07-26
申请号：US13435362
申请日：2012-03-30
CPC分类号： H01L23/66 , H01L2223/6627 , H01L2223/6677 , H01L2924/0002 , H01L2924/09701 , H01L2924/1903 , H01P5/107 , H01Q1/2283 , H01Q1/52 , H01Q9/0407 , H01Q13/06 , H01L2924/00
摘要： Some embodiments herein relate to a transmitter. The transmitter includes an integrated circuit (IC) package including a first antenna configured to radiate a first electromagnetic signal therefrom. A printed circuit board (PCB) substrate includes a waveguide configured to receive the first electromagnetic signal and to generate a waveguide signal based thereon. A second antenna can be electrically coupled to the waveguide and can radiate a second electromagnetic signal that corresponds to the waveguide signal. Other devices and methods are also disclosed.
摘要翻译： 本文中的一些实施例涉及发射机。 发射机包括集成电路（IC）封装，其包括被配置为从其辐射第一电磁信号的第一天线。 印刷电路板（PCB）基板包括配置为接收第一电磁信号并基于其产生波导信号的波导。 第二天线可以电耦合到波导并且可以辐射对应于波导信号的第二电磁信号。 还公开了其它装置和方法。
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