公开(公告)号：US20130043537A1

公开(公告)日：2013-02-21

申请号：US13583409

申请日：2011-03-09

Applicant: Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

Inventor： Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/14658 ,  H01L21/225 ,  H01L21/2652 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1443 ,  H01L27/1461 ,  H01L27/14612 ,  H01L29/66477 ,  H01L29/78648 ,  H01L29/8611

Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

公开(公告)号：US08362562B2

公开(公告)日：2013-01-29

申请号：US12659947

申请日：2010-03-25

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L27/1203 ,  H01L21/823814 ,  H01L21/823878

Abstract: In a semiconductor device of a silicon on insulator (SOI) structure having uniform transistor properties, a first distance between a gate electrode forming position of an N type transistor and an end of a P type semiconductor region is greater than a second distance between a gate electrode forming position of the P type transistor and an edge of the N type semiconductor region.

Abstract translation: 在具有均匀晶体管特性的绝缘体上硅（SOI）结构的半导体器件中，N型晶体管的栅电极形成位置与P型半导体区域的端部之间的第一距离大于栅极之间的第二距离 P型晶体管的电极形成位置和N型半导体区域的边缘。

公开(公告)号：US08217361B2

公开(公告)日：2012-07-10

申请号：US12230976

申请日：2008-09-09

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: G01J1/42

CPC classification number: G01J1/429 ,  H01L31/02161 ,  H01L31/022408 ,  H01L31/103

Abstract: An ultraviolet sensor has an ultraviolet detection diode having a depletion region 18 formed in an Si layer 16 on an insulating layer 14, an interlayer insulating film 20 formed on the ultraviolet detection diode, and a wiring 24 formed on the interlayer insulating film 20. An incident angle θ (°) of an incident light entering into the depletion region 18 and a film thickness Tsi (nm) of the depletion region 18 satisfy the following formula (1), which is also shown in FIG. 14. TSi≦TSi/sin θ≦100  (Formula 1)

Abstract translation: 紫外线传感器具有紫外线检测二极管，其具有形成在绝缘层14上的Si层16中的耗尽区18，形成在紫外检测二极管上的层间绝缘膜20以及形成在层间绝缘膜20上的布线24。 入射角度和角度; 入射到耗尽区18的入射光的（°）和耗尽区18的膜厚Tsi（nm）满足下面的公式（1），其也在图1中示出。 TSi＆nlE; TSi / sin＆Thetas;＆nlE; 100（公式1）

公开(公告)号：US08049291B2

公开(公告)日：2011-11-01

申请号：US12048239

申请日：2008-03-14

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14623 ,  H01L27/14632 ,  H01L27/14645

Abstract: A sensor includes a substrate provided with a circuit element forming region and a photodiode forming region, the substrate having a silicon substrate, an insulating layer on the silicon substrate, and a silicon layer on the insulating layer; a photodiode in the silicon layer; a circuit element in the silicon layer; a first interlayer insulating film formed over the silicon layer; a first light-shielding film on the first interlayer film and having an opening in the photodiode forming region; and a first inter-region light-shielding plug arranged between the two regions, for connecting the silicon substrate and the first light-shielding film.

Abstract translation: 传感器包括设置有电路元件形成区域和光电二极管形成区域的基板，所述基板具有硅基板，硅基板上的绝缘层和绝缘层上的硅层; 硅层中的光电二极管; 硅层中的电路元件; 形成在所述硅层上的第一层间绝缘膜; 在所述第一层间膜上具有在所述光电二极管形成区域中具有开口的第一遮光膜; 以及布置在两个区域之间的用于连接硅衬底和第一屏蔽膜的第一区域间屏蔽插头。

公开(公告)号：US20090078880A1

公开(公告)日：2009-03-26

申请号：US12230976

申请日：2008-09-09

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: G01J1/42

CPC classification number: G01J1/429 ,  H01L31/02161 ,  H01L31/022408 ,  H01L31/103

Abstract: An ultraviolet sensor has an ultraviolet detection diode having a depletion region 18 formed in an Si layer 16 on an insulating layer 14, an interlayer insulating film 20 formed on the ultraviolet detection diode, and a wiring 24 formed on the interlayer insulating film 20. An incident angle θ (°) of an incident light entering into the depletion region 18 and a film thickness Tsi (nm) of the depletion region 18 satisfy the following formula (1), which is also shown in FIG. 14. TSi≦TSi/sin θ≦100   (Formula 1)

Abstract translation: 紫外线传感器具有紫外线检测二极管，其具有形成在绝缘层14上的Si层16中的耗尽区18，形成在紫外检测二极管上的层间绝缘膜20以及形成在层间绝缘膜20上的布线24。 进入耗尽区18的入射光的入射角θ（°）和耗尽区18的膜厚Tsi（nm）满足下面的公式（1），其也在图1中示出。 TSi <= TSi /sinθ<= 100（公式1）<？in-line-formula description =“In-line-formula description =”In-line-formula description = 行公式“end =”tail“？>

公开(公告)号：US20080185651A1

公开(公告)日：2008-08-07

申请号：US12007318

申请日：2008-01-09

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L27/0266 ,  H01L29/78

Abstract: An SOI type semiconductor device having a silicon substrate and a buried oxide layer formed on the silicon substrate includes an internal circuit formed in a first region having at least one FD type transistor having a SOI structure, the internal circuit performing a function of the semiconductor device and a protection circuit formed in a second region having at least one PD type transistor having a SOI structure, the protection circuit protecting the internal circuit from electro static damage.

Abstract translation: 具有在硅衬底上形成的硅衬底和掩埋氧化层的SOI型半导体器件包括形成在具有SOI结构的至少一个FD型晶体管的第一区域中的内部电路，该内部电路执行半导体器件的功能 以及形成在具有至少一个具有SOI结构的PD型晶体管的第二区域中的保护电路，所述保护电路保护所述内部电路免受静电损坏。

公开(公告)号：US07205190B2

公开(公告)日：2007-04-17

申请号：US10963835

申请日：2004-10-14

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/8238

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention adequately activates a substrate contact region of a support substrate without substantially changing the conventional SOI-CMOS device formation process. An exposed face of the support substrate is formed in an element isolation region of a layered substrate, which includes a support substrate having a first semiconductor layer, an insulating layer provided on the support substrate, and a second semiconductor layer provided on the insulating layer, by etching away the insulating layer and the second semiconductor layer. A substrate contact region is then formed in the support substrate by performing ion implantation from the side of the exposed face of the support substrate. Thereafter, an element isolation insulation layer is formed on the exposed face of the support substrate and a gate oxide film and a gate electrode are formed on the remaining second semiconductor layer. In addition, drain and source regions are formed by performing the ion implantation to the remaining second semiconductor layer with the gate electrode serving as a mask. Annealing to activate the substrate contact region, the drain region and the source region is then performed. Thereafter, a metal layer with a high melting point is formed on the drain and source regions and the metal layer is silicided through heat treatment.

Abstract translation: 本发明充分激活支撑衬底的衬底接触区域，而基本上不改变传统的SOI-CMOS器件形成过程。 支撑基板的露出面形成在层叠基板的元件隔离区域中，该层叠基板包括具有第一半导体层的支撑基板，设置在支撑基板上的绝缘层，以及设置在绝缘层上的第二半导体层， 通过蚀刻掉绝缘层和第二半导体层。 然后通过从支撑衬底的暴露面的侧面进行离子注入，在支撑衬底中形成衬底接触区域。 此后，在支撑基板的露出面上形成元件隔离绝缘层，在剩余的第二半导体层上形成栅氧化膜和栅电极。 此外，通过以栅电极作为掩模对剩余的第二半导体层进行离子注入来形成漏极和源极区。 然后进行退火以激活基板接触区域，漏极区域和源极区域。 此后，在漏极和源极区域上形成具有高熔点的金属层，并且通过热处理将金属层硅化。

公开(公告)号：US06849883B2

公开(公告)日：2005-02-01

申请号：US10392930

申请日：2003-03-21

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/161 ,  H01L31/072

CPC classification number: H01L21/823412 ,  H01L27/088 ,  H01L29/1054

Abstract: A MOSFET device including a semiconductor substrate, an SiGe layer provided on top of the semiconductor substrate, an Si layer provided on top of the SiGe layer; and a first isolation region for separating the Si layer into a first region and a second region, wherein the Si layer in the second region is turned into an Si epitaxial layer greater in thickness than the Si layer in the first region. The MOSFET device further includes at least one first MOSFET with the Si layer in the first region serving as a strained Si channel, and at least one second MOSFET with the Si epitaxial layer serving as an Si channel.

Abstract translation: 包括半导体衬底的MOSFET器件，设置在半导体衬底顶部的SiGe层，设置在SiGe层顶部的Si层; 以及用于将Si层分离成第一区域和第二区域的第一隔离区域，其中第二区域中的Si层变成比第一区域中的Si层厚度更大的Si外延层。 MOSFET器件还包括至少一个第一MOSFET，其中第一区域中的Si层用作应变Si沟道，以及至少一个第二MOSFET，其中Si外延层用作Si沟道。

公开(公告)号：US06075270A

公开(公告)日：2000-06-13

申请号：US126844

申请日：1998-07-31

Applicant: Masao Okihara ,  Hidetsugu Uchida

Inventor： Masao Okihara ,  Hidetsugu Uchida

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L29/66477 ,  H01L21/2815 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7834 ,  H01L21/28114 ,  H01L21/28123

Abstract: A field effect transistor and a method for forming the field effect transistor are made up of a source region which is formed on the substrate, a drain region which is formed on the substrate, a stepped portion which is formed in the substrate between the source region and the drain region, a gate insulating film which is formed on the stepped portion of the substrate, and a gate electrode which is formed on the gate insulating film, wherein, a thickness of the gate insulating film near the drain region, which is less than that of the gate insulating film on a channel region defined in the substrate between the source region and the drain region. Accordingly, the field effect transistor and a method for forming the field effect transistor can prevent degradation of transistor characteristics because of a hot carrier effect.

Abstract translation: 场效应晶体管和形成场效应晶体管的方法由形成在基板上的源极区域，形成在基板上的漏极区域，形成在源极区域之间的基板中的台阶部分 漏极区域，形成在基板的阶梯部上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极，其中，漏极区域附近的栅极绝缘膜的厚度较小 比在源极区域和漏极区域之间的衬底中限定的沟道区域上的栅极绝缘膜的栅极绝缘膜的厚度大。 因此，场效应晶体管和形成场效应晶体管的方法可以防止由于热载流子效应导致的晶体管特性的劣化。

公开(公告)号：US08963246B2

公开(公告)日：2015-02-24

申请号：US13583409

申请日：2011-03-09

Applicant: Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

Inventor： Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

IPC: H01L27/12 ,  H01L21/265 ,  H01L27/144 ,  H01L29/861 ,  H01L29/786

CPC classification number: H01L27/14658 ,  H01L21/225 ,  H01L21/2652 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1443 ,  H01L27/1461 ,  H01L27/14612 ,  H01L29/66477 ,  H01L29/78648 ,  H01L29/8611

Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Abstract translation: 提供了半导体器件和半导体器件的制造方法。 在由高电阻N型衬底形成的N型半导体层内，形成P型阱扩散层和P型提取层，并将其固定为接地电位。 由此，在P型阱扩散层侧扩散的耗尽层未达到P型阱扩散层与埋入氧化膜之间的层间界限。 因此，P型阱扩散层的表面周围的电位保持在接地电位。 因此，当将电压施加到N型半导体层和阴极的背面时，形成为P型半导体层的MOS型半导体的沟道区域不被激活。 由此，能够抑制由于晶体管的栅电极引起的控制而发生的漏电流。