公开(公告)号：US09697897B2

公开(公告)日：2017-07-04

申请号：US14331274

申请日：2014-07-15

Applicant: Michael A Sadd ,  Anirban Roy

Inventor： Michael A Sadd ,  Anirban Roy

IPC: G11C14/00

CPC classification number: G11C14/0063

Abstract: A memory device includes a volatile memory cell, a non-volatile memory cell, and a transfer system connected between the volatile memory cell and the non-volatile memory cell. The transfer circuit allows data transfer from the volatile memory cell to the non-volatile memory cell when the memory device is operating in a first mode, and from the non-volatile memory cell to the volatile memory cell when the memory device is operating in a second mode.

公开(公告)号：US20160019964A1

公开(公告)日：2016-01-21

申请号：US14331274

申请日：2014-07-15

Applicant: MICHAEL A. SADD ,  ANIRBAN ROY

Inventor： MICHAEL A. SADD ,  ANIRBAN ROY

IPC: G11C14/00

CPC classification number: G11C14/0063

Abstract: A memory device includes a volatile memory cell, a non-volatile memory cell, and a transfer system connected between the volatile memory cell and the non-volatile memory cell. The transfer circuit allows data transfer from the volatile memory cell to the non-volatile memory cell when the memory device is operating in a first mode, and from the non-volatile memory cell to the volatile memory cell when the memory device is operating in a second mode.

Abstract translation: 存储器件包括易失性存储器单元，非易失性存储器单元和连接在易失性存储器单元和非易失性存储器单元之间的传输系统。 当存储器设备在第一模式下操作时，传送电路允许从易失性存储器单元到非易失性存储器单元的数据传输，并且当存储器设备工作在第一模式时，从非易失性存储器单元到易失性存储器单元 第二模式。

公开(公告)号：US20120241909A1

公开(公告)日：2012-09-27

申请号：US13070049

申请日：2011-03-23

Applicant: Tushar P. Merchant ,  Michael A. Sadd

Inventor： Tushar P. Merchant ,  Michael A. Sadd

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/92 ,  H01L29/94

Abstract: A process and device structure is provided for increasing capacitance density of a capacitor structure. A sandwich capacitor is provided in which a bottom silicon-containing conductor plate is formed with holes or cavities, upon which an oxide layer and a top silicon-containing layer conductor is formed. The holes or cavities provide additional capacitive area, thereby increasing capacitance per footprint area of the capacitor structure. The holes can form, for example, a line structure or a waffle-like structure in the bottom conductor plate. Etching techniques used to form the holes in the bottom conductor plate can also result in side wall tapering of the holes, thereby increasing the surface area of the silicon-containing layer defined by the holes. In addition, depth of holes can be adjusted through timed etching to further adjust capacitive area.

Abstract translation: 提供了一种用于增加电容器结构的电容密度的工艺和器件结构。 提供一种夹层电容器，其中底部含硅导电板形成有孔或空腔，在其上形成氧化物层和顶部含硅层导体。 孔或腔提供附加的电容区域，从而增加电容器结构的每个覆盖区域的电容。 孔可以形成例如底部导体板中的线结构或华夫饼状结构。 用于在底部导体板中形成孔的蚀刻技术还可导致孔的侧壁渐缩，从而增加由孔限定的含硅层的表面积。 此外，可以通过定时蚀刻来调整孔的深度，以进一步调整电容面积。

公开(公告)号：US07800164B2

公开(公告)日：2010-09-21

申请号：US12397849

申请日：2009-03-04

Applicant: Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

Inventor： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

IPC: H01L29/792

CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/7881 ,  Y10S977/773

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

Abstract translation: 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

公开(公告)号：US07456465B2

公开(公告)日：2008-11-25

申请号：US11240240

申请日：2005-09-30

Applicant: Erwin J. Prinz ,  Michael A. Sadd ,  Robert F. Steimle

Inventor： Erwin J. Prinz ,  Michael A. Sadd ,  Robert F. Steimle

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/42332

Abstract: A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.

Abstract translation: 分离栅极存储单元具有选择栅极，控制栅极和电荷存储结构。 选择栅极包括位于控制栅极上方的第一部分和不位于控制栅极上方的第二部分。 在一个示例中，选择栅极的第一部分具有与控制栅极的侧壁对齐并与电荷存储结构的侧壁对准的侧壁。 在一个示例中，控制栅极具有p型导电性。 在一个示例中，门可以通过热载流子注入操作来编程，并且可以通过隧道操作来擦除。

公开(公告)号：US07279997B2

公开(公告)日：2007-10-09

申请号：US11250994

申请日：2005-10-14

Applicant: Sriram S. Kalpat ,  Leo Mathew ,  Mohamed S. Moosa ,  Michael A. Sadd ,  Hector Sanchez

Inventor： Sriram S. Kalpat ,  Leo Mathew ,  Mohamed S. Moosa ,  Michael A. Sadd ,  Hector Sanchez

IPC: H03L7/099

CPC classification number: H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0995

Abstract: A voltage controlled oscillator (VCO) has a plurality of series-connected inverters. Within each inverter a first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series-connected inverters, and a second control electrode for receiving a first bias signal. A second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

公开(公告)号：US20090042349A1

公开(公告)日：2009-02-12

申请号：US12254294

申请日：2008-10-20

Applicant: Erwin J. Prinz ,  Michael A. Sadd ,  Robert F. Steimle

Inventor： Erwin J. Prinz ,  Michael A. Sadd ,  Robert F. Steimle

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/42332

Abstract: A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.

Abstract translation: 分离栅极存储单元具有选择栅极，控制栅极和电荷存储结构。 选择栅极包括位于控制栅极上方的第一部分和不位于控制栅极上方的第二部分。 在一个示例中，选择栅极的第一部分具有与控制栅极的侧壁对齐并与电荷存储结构的侧壁对准的侧壁。 在一个示例中，控制栅极具有p型导电性。 在一个示例中，门可以通过热载流子注入操作来编程，并且可以通过隧道操作来擦除。

公开(公告)号：US06847548B2

公开(公告)日：2005-01-25

申请号：US10601256

申请日：2003-06-20

Applicant: Craig T. Swift ,  Michael A. Sadd

Inventor： Craig T. Swift ,  Michael A. Sadd

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/0491 ,  G11C16/0475

Abstract: A memory has an array made up of transistors that have two charge storage regions between the channel and control gate. Each bit is made up of two charge storage regions that are from different transistors. A bit is written by first erasing all of the storage locations and then writing one of the charge storage locations that make up the bit. A pair of charge storage locations, one erased and the other programmed, is identified for each bit. The logic state of the bit is read by comparing the charge stored in the two charge storage locations that make up the bit. This comparison is achieved by generating signals representative of the charge present in the two charge storage locations. These signals are then coupled to a sense amplifier that functions as a comparator. This avoids many problems that accompany comparisons to a fixed reference.

Abstract translation: 存储器具有由在通道和控制栅极之间具有两个电荷存储区域的晶体管组成的阵列。 每个位由来自不同晶体管的两个电荷存储区组成。 首先擦除所有存储位置，然后写入构成该位的电荷存储位置之一，写入一位。 每一位识别一对电荷存储单元，一个被擦除，另一个编程。 通过比较存储在构成该位的两个电荷存储位置中的电荷来读取该位的逻辑状态。 该比较通过产生表示两个电荷存储位置中存在的电荷的信号来实现。 这些信号然后被耦合到用作比较器的读出放大器。 这避免了许多与固定参考比较的问题。

公开(公告)号：US07517747B2

公开(公告)日：2009-04-14

申请号：US11530053

申请日：2006-09-08

Applicant: Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

Inventor： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

IPC: H01L21/8238

CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/7881 ,  Y10S977/773

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

Abstract translation: 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

公开(公告)号：US20080121967A1

公开(公告)日：2008-05-29

申请号：US11530054

申请日：2006-09-08

Applicant: Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

Inventor： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/513 ,  H01L29/7881

Abstract: A method of forming a semiconductor device, which is preferably a memory cell, includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, wherein each of the plurality of discrete storage elements has a diameter value that is approximately equal to each other, and forming a second dielectric layer over the plurality of discrete storage elements, wherein the second dielectric layer has a thickness, wherein the ratio of the thickness of the second dielectric to the diameter value is less than approximately 0.8. The spacing between the plurality of discrete storage elements may be greater than or equal to approximately the thickness of the second dielectric layer.

Abstract translation: 形成半导体器件的方法，其优选地是存储单元，包括在半导体衬底上形成第一介电层，在第一介电层上形成多个离散存储元件，其中多个离散存储元件中的每一个具有 并且在所述多个分立存储元件上形成第二电介质层，其中所述第二电介质层具有厚度，其中所述第二电介质的厚度与所述直径值的比值小于 约0.8。 多个离散存储元件之间的间隔可以大于或等于第二电介质层的厚度。