公开(公告)号：US07072198B2

公开(公告)日：2006-07-04

申请号：US10681887

申请日：2003-10-09

Applicant: James L. Krug ,  David W. Evans ,  J. Patrick Kawamura

Inventor： James L. Krug ,  David W. Evans ,  J. Patrick Kawamura

IPC: H02M7/217

CPC classification number: H02M3/156 ,  H02M2001/0025

Abstract: A switching mode converter, having a switching transistor and an inductor, has a discontinuity detector coupled to the inductor which detects when the converter enters the discontinuous mode. The discontinuity detector determines the portion of the cycle of the switching transistor in which the converter is in the discontinuous mode. A feedback controller is coupled to the output of the converter and to the discontinuity detector which alters a feedback control signal of the converter.

Abstract translation: 具有开关晶体管和电感器的开关模式转换器具有耦合到电感器的不连续检测器，其检测转换器何时进入不连续模式。 不连续检测器确定转换器处于不连续模式的开关晶体管的周期部分。 反馈控制器耦合到转换器的输出和改变转换器的反馈控制信号的不连续检测器。

公开(公告)号：US06240047B1

公开(公告)日：2001-05-29

申请号：US09537454

申请日：2000-03-27

Applicant: Jeffrey E. Koelling ,  J. Patrick Kawamura

Inventor： Jeffrey E. Koelling ,  J. Patrick Kawamura

IPC: G11C800

CPC classification number: G11C7/1072 ,  G11C7/1078

Abstract: A memory circuit for operating synchronously with a system clock signal is designed with a memory array (250, 252, 254, 256) having a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits (502) produces a select signal at a respective column select line (108) in response to a first column address signal. A plurality of sense amplifier circuits (202) is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line (203). A control terminal of each select transistor of a group of sense amplifier circuits is connected to the respective column select line. A data sequence circuit (218) is coupled to receive four data bits from four respective data lines (210, 212, 214, 216) in response to a first cycle of the system clock signal. The data sequence circuit produces four ordered data bits in response to a control signal and a second column address signal. A register circuit (220) is coupled to receive the four ordered data bits. The register circuit produces a sequence of the four ordered data bits in response to a plurality of cycles of the system clock signal after the first cycle of the system clock signal.

Abstract translation: 用于与系统时钟信号同步操作的存储器电路被设计为具有以行和列排列的多个存储器单元的存储器阵列（250,252,254,256）。 响应于第一列地址信号，多列列解码电路（502）的每列解码电路在相应的列选择线（108）产生选择信号。 多个读出放大器电路（202）分组布置。 每个读出放大器电路耦合到相应的存储单元列。 每个读出放大器电路包括用于将读出放大器耦合到相应的数据线（203）的选择晶体管。 一组读出放大器电路的每个选择晶体管的控制端子连接到相应的列选择线。 数据序列电路（218）被耦合以响应于系统时钟信号的第一周期从四个相应的数据线（210,212,214,216）接收四个数据位。 数据序列电路响应于控制信号和第二列地址信号产生四个有序的数据位。 寄存器电路（220）被耦合以接收四个有序的数据位。 寄存器电路在系统时钟信号的第一周期之后响应于系统时钟信号的多个周期而产生四个有序数据位的序列。

公开(公告)号：US5896310A

公开(公告)日：1999-04-20

申请号：US998338

申请日：1997-12-24

Applicant: J. Patrick Kawamura ,  Harvey A. Vargis

Inventor： J. Patrick Kawamura ,  Harvey A. Vargis

IPC: G11C11/413 ,  G11C5/02 ,  G11C5/14 ,  G11C7/10 ,  G11C8/10 ,  G11C11/401 ,  G11C5/06

CPC classification number: G11C8/10 ,  G11C5/025 ,  G11C5/14 ,  G11C7/10

Abstract: A memory configuration (20) which includes a first and second bank (B0, B1). Both bank arrays comprises a plurality of wordlines (WLs) and bitlines (BLs). The memory configuration further includes a plurality of column decoder circuits (CDEC0-CDEC7), and a plurality of y-select conductors (C0-C15) generally parallel to the plurality of bitlines of the first bank array. Each of the plurality of y-select conductors is operable to be selected by one of the plurality of column decoder circuits in response to a column address. The memory configuration further includes a plurality of column factor conductors (F0.sub.I, F1.sub.I, F2.sub.I) formed in a direct periphery area existing between the first and second bank arrays. Still further, the memory configuration includes a power conductor (PDD.sub.I) formed between the first and second bank arrays, and aligned generally parallel to the plurality of wordlines of the first and second bank arrays. Lastly, the memory configuration includes a plurality of programmable conductors (PC0-PC7) disposed between and generally parallel to the plurality of y-select conductors. The programmable conductors are formed such that a first portion of each of the plurality of programmable conductors overlies the first bank array and a second portion of each of the plurality of programmable conductors extends toward the direct periphery. Each of the plurality of programmable conductors may be selected for connecting to a corresponding one of the plurality of column factor conductors or to the power conductor.

Abstract translation: 一种包括第一和第二存储体（B0，B1）的存储器配置（20）。 两个存储体阵列包括多个字线（WL）和位线（BL）。 存储器配置还包括多个列解码器电路（CDEC0-CDEC7）和大体平行于第一存储体阵列的多个位线的多个y选择导体（C0-C15）。 响应于列地址，多个y选择导体中的每一个可操作以由多个列解码器电路中的一个选择。 存储器配置还包括形成在存在于第一和第二存储体阵列之间的直接周边区域中的多个列因子导体（F0I，F1I，F2I）。 此外，存储器配置包括形成在第一和第二存储体阵列之间并且大致平行于第一和第二存储体阵列的多个字线的电源导体（PDDI）。 最后，存储器配置包括多个可编程导体（PC0-PC7），其设置在多个y选择导体之间并且大致平行于多个y选择导体。 可编程导体形成为使得多个可编程导体中的每一个的第一部分覆盖第一组阵列，并且多个可编程导体中的每一个的第二部分朝向直接周边延伸。 可以选择多个可编程导体中的每一个用于连接到多个列因子导体中的相应一个或电力导体。

公开(公告)号：US5483205A

公开(公告)日：1996-01-09

申请号：US369945

申请日：1995-01-09

Applicant: J. Patrick Kawamura

Inventor： J. Patrick Kawamura

IPC: G11C11/407 ,  H03K3/012 ,  H03K3/03 ,  H03K3/354 ,  H03K19/0948 ,  H03B5/24 ,  H03K5/003

CPC classification number: H03K3/03 ,  H03K3/012

Abstract: An oscillator circuit (150) is designed with a reference circuit (102), responsive to a first voltage, for producing a second voltage. An oscillator (108), responsive to the second voltage, produces a first output signal having a magnitude less than a magnitude of the first voltage. A level translator (114), responsive to the first output signal, produces a second output signal having a magnitude greater than the magnitude of the first output signal. Since the oscillator produces the first output signal with a magnitude less than the magnitude of the first voltage, power consumption is reduced with respect to an oscillator operating at the first voltage. The magnitude of the first output signal is increased by the level translator to a desired magnitude of the second output signal.

Abstract translation: 振荡器电路（150）被设计有响应于第一电压的用于产生第二电压的参考电路（102）。 响应于第二电压的振荡器（108）产生具有小于第一电压幅度的幅度的第一输出信号。 响应于第一输出信号的电平转换器（114）产生具有大于第一输出信号幅度的幅度的第二输出信号。 由于振荡器产生的幅度小于第一电压的幅度的第一输出信号，所以相对于以第一电压工作的振荡器的功耗降低。 第一输出信号的幅度由电平转换器增加到第二输出信号的期望幅度。

公开(公告)号：US06686729B1

公开(公告)日：2004-02-03

申请号：US10271121

申请日：2002-10-15

Applicant: J. Patrick Kawamura ,  James L. Krug ,  David W. Evans

Inventor： J. Patrick Kawamura ,  James L. Krug ,  David W. Evans

IPC: G05F140

CPC classification number: H03K17/04163 ,  H02M3/155 ,  H02M2001/0048 ,  H03K2217/0036 ,  Y02B70/1491

Abstract: A DC/DC switching regulator has a semiconductor switch coupled to an inductor, a first capacitor and a rectifier. A circuit to improve the switching efficiency of the semiconductor switch has a transmission gate coupled between the gate of the semiconductor switch and a second capacitor. The transmission gate is turned ON only when the gate of the semiconductor switch is about to make a positive or negative transition and isolated from the first and second voltage sources. A portion of the charge stored in the parasitic capacitance of the gate of the semiconductor switch can be stored in the second capacitor and reused to partially drive the semiconductor switch from the second to the first ON/OFF state. A further embodiment employs this technique with a synchronous rectifier in the regulator circuit.

Abstract translation: DC / DC开关调节器具有耦合到电感器，第一电容器和整流器的半导体开关。 用于提高半导体开关的开关效率的电路具有耦合在半导体开关的栅极和第二电容器之间的传输栅极。 只有当半导体开关的栅极将要进行正或负的转换并且与第一和第二电压源隔离时，传输门才被接通。 存储在半导体开关的栅极的寄生电容中的电荷的一部分可以存储在第二电容器中并重新用于将半导体开关从第二导通/断开状态部分地驱动。 另一实施例在调节器电路中采用该技术与同步整流器。

公开(公告)号：US06515880B1

公开(公告)日：2003-02-04

申请号：US10090175

申请日：2001-10-19

Applicant: David W. Evans ,  J. Patrick Kawamura ,  James L. Krug

Inventor： David W. Evans ,  J. Patrick Kawamura ,  James L. Krug

IPC: H02M710

CPC classification number: H02M1/36

Abstract: Startup operation of a DC/DC switching regulator is controlled by providing a first signal (MAXDC) whose waveform has a duty cycle that varies over time, providing a second signal (620, 622) indicative of a load condition of the regulator, and combining the first and second signals to produce a third signal (312, 311). The third signal is used to control a power switch (231, 324) of the regulator.

Abstract translation: 通过提供其波形具有随时间变化的占空比的第一信号（MAXDC）来控制DC / DC开关调节器的启动操作，提供指示调节器的负载状态的第二信号（620,622），以及组合 第一和第二信号以产生第三信号（312,311）。 第三个信号用于控制调节器的电源开关（231,324）。

公开(公告)号：US5959487A

公开(公告)日：1999-09-28

申请号：US858072

申请日：1997-05-16

Applicant: J. Patrick Kawamura

Inventor： J. Patrick Kawamura

IPC: G01R31/28 ,  H03K5/13 ,  H03K5/26 ,  H03H11/26

CPC classification number: H03K5/131 ,  H03K5/26

Abstract: A circuit is designed with a reference circuit (200) for generating a reference signal. The reference signal determines a reference period. A delay circuit (208, 212, 216) responsive to the reference signal produces a delay signal. A control circuit (248, 254, 258, 260, 262) responsive to the delay signal produces a control signal. The delay circuit emulates the speed of an integrated circuit for the reference period. Control signals from the control circuit compensate the integrated circuit performance for measured circuit speed variations.

Abstract translation: 电路设计有用于产生参考信号的参考电路（200）。 参考信号确定参考周期。 响应于参考信号的延迟电路（208,212,216）产生延迟信号。 响应于延迟信号的控制电路（248,254,258,260,262）产生控制信号。 延迟电路在参考周期模拟集成电路的速度。 来自控制电路的控制信号补偿了测量电路速度变化的集成电路性能。

公开(公告)号：US20130257171A1

公开(公告)日：2013-10-03

申请号：US13851892

申请日：2013-03-27

Applicant: ROSS E. TEGGATZ ,  JONATHAN KNIGHT ,  PATRICK KAWAMURA ,  WAYNE T. CHEN

Inventor： Ross E. Teggatz ,  Jonathan Knight ,  Patrick Kawamura ,  Wayne T. Chen

IPC: H04B5/00 ,  H01Q3/24 ,  H01Q3/02 ,  H01Q1/50

CPC classification number: H04B5/0037 ,  H01Q1/50 ,  H01Q3/02 ,  H01Q3/24 ,  H01Q7/00 ,  H01Q21/28 ,  H04B5/0087

Abstract: A resonant circuit dynamic optimization system is described herein that can exhibit improved system charging functionality, can have multi-input charging functionality, and can improve the efficiency and speed of charging electronic devices. The resonant circuit dynamic optimization system can comprise at least one antenna configured to receive or transmit an electromagnetic signal, at least one variable component, and at least one dynamic adjustment circuit. The dynamic adjustment circuit can adjust the variable component to thereby modify the power transfer efficiency of the electromagnetic signal.

Abstract translation: 本文描述了可以呈现改进的系统充电功能的谐振电路动态优化系统，可以具有多输入充电功能，并且可以提高对电子设备的充电的效率和速度。 谐振电路动态优化系统可以包括被配置为接收或发送电磁信号，至少一个可变分量和至少一个动态调整电路的至少一个天线。 动态调整电路可以调节可变分量，从而改变电磁信号的功率传递效率。

公开(公告)号：US06259310B1

公开(公告)日：2001-07-10

申请号：US08449409

申请日：1995-05-23

Applicant: J. Patrick Kawamura

Inventor： J. Patrick Kawamura

IPC: G05F302

CPC classification number: H02M3/073 ,  G05F3/205 ,  H02M2003/071

Abstract: A VBB voltage generator unit for biasing of the semiconductor chip substrate is comprised of five basic elements, a standard p-channel substrate pump unit a pump supply voltage switch, a VBB level control logic unit, a high and low frequency oscillators unit, and a Vperi voltage divider unit for generating a fractional Vperi voltage. The substrate pump is a standard two-phase p-channel coupling pump. In response to appropriate control signals, p-channel coupling pump can provide a plurality of VBB voltage levels in response to a single oscillator frequency. The VBB voltage levels can be correlated, via the control signals, to the operational mode of the device.

Abstract translation: 用于偏置半导体芯片基板的VBB电压发生器单元包括五个基本元件，标准p沟道基板泵单元，泵电源电压开关，VBB电平控制逻辑单元，高低频振荡器单元和 Vperi分压器单元，用于产生分数Vperi电压。 衬底泵是标准的两相p沟道耦合泵。 响应于适当的控制信号，p沟道耦合泵可以响应于单个振荡器频率而提供多个VBB电压电平。 VBB电压电平可以通过控制信号与设备的工作模式相关联。

公开(公告)号：US06252466B1

公开(公告)日：2001-06-26

申请号：US09547818

申请日：2000-04-11

Applicant: J. Patrick Kawamura

Inventor： J. Patrick Kawamura

IPC: H03L7089

CPC classification number: H03L7/095 ,  H03L7/0891 ,  Y10S331/02

Abstract: PLL power up detector includes a capacitor coupled to a charging circuit. The capacitor is charged to a level responsive to the pulse width of the UP and DOWN signals produced by the PFD circuit included in the PLL circuit. When the PLL is near or at the locked state, the UP and DOWN signals will exhibit short high-going pulses or remain at ground level, allowing charger circuit increase the voltage on the capacitor. The Schmitt trigger circuit senses the voltage level on the capacitor and outputs a signal indicating the PLL is near or at the locked state. The Schmitt trigger output signal is coupled to a counter circuit to further validate the lock state of the PLL. The Schmitt trigger output signal must remain at the locked state for n-consecutive reference clock cycles before the PLL power-up signal, is asserted. When the power-up signal is asserted, the charging circuit is disabled and PLL power up detector will not consume quiescent current.

Abstract translation: PLL上电检测器包括耦合到充电电路的电容器。 电容器被充电到响应于包括在PLL电路中的PFD电路产生的UP和DOWN信号的脉冲宽度的电平。 当PLL接近或处于锁定状态时，UP和DOWN信号将呈现短暂的高电平脉冲或保持在地电平，从而允许充电器电路增加电容器上的电压。 施密特触发电路检测电容器上的电压电平，并输出指示PLL接近或处于锁定状态的信号。 施密特触发器输出信号耦合到计数器电路，以进一步验证PLL的锁定状态。 在施加PLL上电信号之前，施密特触发输出信号必须保持在n个连续参考时钟周期的锁定状态。 当上电信号置位时，充电电路被禁止，PLL上电检测器不会消耗静态电流。