公开(公告)号：US20100038795A1

公开(公告)日：2010-02-18

申请号：US12542540

申请日：2009-08-17

申请人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

发明人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

摘要翻译： 根据实施例的制造半导体器件的方法包括在基底层上形成具有恒定线宽度和第二图案的线性部分的第一图案，第二图案包括靠近第一图案的线性部分的部分和部分离开 从第一图案的直线部分和独立于第一图案构成闭环形状，或者处于连接到第一图案的状态，并且在第二图案的部分处远离线形部分进行闭环切割 第一种模式

公开(公告)号：US20120241834A1

公开(公告)日：2012-09-27

申请号：US13234052

申请日：2011-09-15

申请人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Ryota Aburada ,  Chikaaki Kodama

发明人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Ryota Aburada ,  Chikaaki Kodama

IPC分类号： H01L27/088 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/768 ,  H01L21/76816 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

摘要： According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(λ/NA) or less when an exposure wavelength of an exposure device is λ, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

摘要翻译： 根据一个实施例，半导体器件包括从元件形成区域延伸到绘图区域并且与元件形成区域中的半导体元件连接并且与绘图区域中的触点连接的互连。 基于在牺牲层的侧表面上匹配第n个（其中n是1或更大的整数）的第一侧壁膜的图案的第（n + 1）第二侧壁膜的图案形成互连。 当曝光装置的曝光波长为λ时，在元件形成区域中匹配互连的互连宽度的第一尺寸和元件形成区域中的互连间隔为（k1 / 2n）×（λ/ NA）或更小，透镜的数值孔径 的曝光装置为NA，处理参数为k1。 在绘图区域中匹配互连间隔的第二维大于第一维度。

公开(公告)号：US20100241261A1

公开(公告)日：2010-09-23

申请号：US12705640

申请日：2010-02-15

申请人： Takafumi TAGUCHI ,  Toshiya Kotani ,  Michiya Takimoto ,  Fumiharu Nakajima ,  Ryota Aburada ,  Hiromitsu Mashita ,  Katsumi Iyanagi ,  Chikaaki Kodama

发明人： Takafumi TAGUCHI ,  Toshiya Kotani ,  Michiya Takimoto ,  Fumiharu Nakajima ,  Ryota Aburada ,  Hiromitsu Mashita ,  Katsumi Iyanagi ,  Chikaaki Kodama

IPC分类号： G05B13/04 ,  G06F17/50 ,  G06F19/00

CPC分类号： G03F1/36

摘要： Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.

摘要翻译： 基于在处理条件下设置的多个处理参数进行OPC处理的设计布局数据执行模式形成模拟。 根据模拟结果提取的风险点计算过程条件的最差条件。 改变设计布局数据或OPC处理，使得当在最坏条件下基于改变的设计布局数据形成图案时，或者改变的OPC处理多个风险点或图案的风险点的风险程度 小于模拟结果。

公开(公告)号：US08183148B2

公开(公告)日：2012-05-22

申请号：US12542540

申请日：2009-08-17

申请人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

发明人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

IPC分类号： H01L21/4763

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

摘要翻译： 根据实施例的制造半导体器件的方法包括在基底层上形成具有恒定线宽度和第二图案的线性部分的第一图案，第二图案包括靠近第一图案的线性部分的部分和部分离开 从第一图案的直线部分和独立于第一图案构成闭环形状，或者处于连接到第一图案的状态，并且在第二图案的部分处远离线形部分进行闭环切割 第一种模式

公开(公告)号：US20110154273A1

公开(公告)日：2011-06-23

申请号：US12964185

申请日：2010-12-09

申请人： Ryota ABURADA ,  Toshiya Kotani

发明人： Ryota ABURADA ,  Toshiya Kotani

IPC分类号： G06F17/50

CPC分类号： H01L21/32139 ,  G03F1/36 ,  G03F1/70 ,  H01L21/0337

摘要： According to one embodiment, in process simulation, it is verified whether sidewall patterns formed on sidewalls of a core material pattern or a transfer pattern formed by transferring the core material pattern form a closed loop. When it is determined as a result of the verification that the sidewall patterns form a closed loop, the mask pattern is changed. When it is determined as a result of the verification that the sidewall patterns do not form a closed loop, the mask pattern is adopted.

摘要翻译： 根据一个实施例，在过程模拟中，验证了形成在芯材料图案的侧壁上的侧壁图案或通过转移芯材料图案形成的转印图案形成闭环。 当确定侧壁图案形成闭环的验证的结果时，改变掩模图案。 当确定作为侧壁图案不形成闭环的验证的结果时，采用掩模图案。

公开(公告)号：US20110069531A1

公开(公告)日：2011-03-24

申请号：US12858986

申请日：2010-08-18

申请人： Ryota ABURADA ,  Toshiya KOTANI ,  Takafumi TAGUCHI ,  Chikaaki KODAMA

发明人： Ryota ABURADA ,  Toshiya KOTANI ,  Takafumi TAGUCHI ,  Chikaaki KODAMA

IPC分类号： G11C11/00 ,  H01L21/02

CPC分类号： H01L27/2481 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/22 ,  G11C13/0004 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1675

摘要： According to one embodiment, a method of manufacturing a nonvolatile semiconductor storage device includes a memory-cell forming step, a first wire forming step, and a second wire forming step. The memory-cell forming step is forming dummy memory cells arranged at a predetermined space apart from an end memory cell located at an end of a group of memory cells set in contact with the same first or second wire among the memory cells, the dummy memory cells having a laminated structure same as that of the memory cells and being set in contact with no second wire.

摘要翻译： 根据一个实施例，制造非易失性半导体存储装置的方法包括存储单元形成步骤，第一线形成步骤和第二线形成步骤。 存储单元形成步骤是形成布置在与存储单元中的与相同的第一或第二布线接触的一组存储单元的一端的端部存储单元隔开的预定空间的虚拟存储单元，该虚拟存储器 电池具有与存储单元的层叠结构相同的层叠结构，并与第二导线接触。

公开(公告)号：US20130126959A1

公开(公告)日：2013-05-23

申请号：US13613473

申请日：2012-09-13

申请人： Ryota Aburada ,  Takashi Obara ,  Toshiya Kotani

发明人： Ryota Aburada ,  Takashi Obara ,  Toshiya Kotani

IPC分类号： H01L27/088 ,  H01L21/302 ,  H01L21/336 ,  H01L29/02

CPC分类号： H01L21/0337 ,  H01L21/32139 ,  H01L27/11582

摘要： According to one embodiment, there are provided a first shaped pattern in which a plurality of first holes are arranged and of which a width is periodically changed along an arrangement direction of the first holes, a second shaped pattern in which a plurality of second holes are arranged and of which a width is periodically changed along an arrangement direction of the second holes, and slits which are formed along the arrangement direction of the first holes and separate the first shaped pattern and the second shaped pattern.

摘要翻译： 根据一个实施例，提供了一种第一成形图案，其中布置多个第一孔并且沿着第一孔的排列方向周期性地改变宽度，第二成形图案中多个第二孔是 沿着第二孔的排列方向周期性地改变宽度，沿着第一孔的排列方向形成并分离第一成形图案和第二成形图案的狭缝。

公开(公告)号：US08336005B2

公开(公告)日：2012-12-18

申请号：US13050864

申请日：2011-03-17

申请人： Takafumi Taguchi ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Fumiharu Nakajima ,  Ryota Aburada ,  Chikaaki Kodama

发明人： Takafumi Taguchi ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Fumiharu Nakajima ,  Ryota Aburada ,  Chikaaki Kodama

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position.

摘要翻译： 根据一个实施例的图案尺寸计算方法计算当在形成在基板上的电路图案的上层中处理电路图案时用作掩模的掩模构件的锥形形状。 该方法基于锥形形状从电路图案上的形状预测位置计算面向掩模构件的打开角度。 该方法根据在形状预测位置处形成的打开角度来计算电路图案的尺寸。

公开(公告)号：US08266552B2

公开(公告)日：2012-09-11

申请号：US12705640

申请日：2010-02-15

申请人： Takafumi Taguchi ,  Toshiya Kotani ,  Michiya Takimoto ,  Fumiharu Nakajima ,  Ryota Aburada ,  Hiromitsu Mashita ,  Katsumi Iyanagi ,  Chikaaki Kodama

发明人： Takafumi Taguchi ,  Toshiya Kotani ,  Michiya Takimoto ,  Fumiharu Nakajima ,  Ryota Aburada ,  Hiromitsu Mashita ,  Katsumi Iyanagi ,  Chikaaki Kodama

IPC分类号： G06F17/50 ,  G06F19/00 ,  G05B13/04

CPC分类号： G03F1/36

摘要： Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.

摘要翻译： 基于在处理条件下设置的多个处理参数进行OPC处理的设计布局数据来执行模式形成模拟。 根据模拟结果提取的风险点计算过程条件的最差条件。 改变设计布局数据或OPC处理，使得当在最坏条件下基于改变的设计布局数据形成图案时，或者改变的OPC处理多个风险点或图案的风险点的风险程度 小于模拟结果。

公开(公告)号：US20110065030A1

公开(公告)日：2011-03-17

申请号：US12880507

申请日：2010-09-13

申请人： Toshiya KOTANI ,  Fumiharu Nakajima ,  Ryota Aburada ,  Takafumi Taguchi ,  Hiromitsu Mashita ,  Michiya Takimoto ,  Chikaaki Kodama

发明人： Toshiya KOTANI ,  Fumiharu Nakajima ,  Ryota Aburada ,  Takafumi Taguchi ,  Hiromitsu Mashita ,  Michiya Takimoto ,  Chikaaki Kodama

IPC分类号： G03F7/20 ,  G06F17/50

CPC分类号： G06F17/5009 ,  G03F1/68 ,  G03F7/70425

摘要： According to one embodiment, a mask pattern determining method includes a mask-pattern dimension variation amount of a first photomask is derived. Moreover, a correspondence relationship between a target dimension value of an on-substrate test pattern formed by using a second photomask and a dimension allowable variation amount of a mask pattern formed on the second photomask is derived. Then, it is determined whether pattern formation is possible with a pattern dimension that needs to be formed when performing the pattern formation on a substrate by using the first photomask based on the mask-pattern dimension variation amount and the correspondence relationship.

摘要翻译： 根据一个实施例，掩模图案确定方法包括导出第一光掩模的掩模图案尺寸变化量。 此外，导出通过使用第二光掩模形成的基板上测试图案的目标尺寸值与形成在第二光掩模上的掩模图案的尺寸允许变化量之间的对应关系。 然后，基于掩模图案尺寸变化量和对应关系，通过使用第一光掩模在基板上进行图案形成时，确定是否可以形成图案尺寸。