公开(公告)号：US20130126959A1

公开(公告)日：2013-05-23

申请号：US13613473

申请日：2012-09-13

申请人： Ryota Aburada ,  Takashi Obara ,  Toshiya Kotani

发明人： Ryota Aburada ,  Takashi Obara ,  Toshiya Kotani

IPC分类号： H01L27/088 ,  H01L21/302 ,  H01L21/336 ,  H01L29/02

CPC分类号： H01L21/0337 ,  H01L21/32139 ,  H01L27/11582

摘要： According to one embodiment, there are provided a first shaped pattern in which a plurality of first holes are arranged and of which a width is periodically changed along an arrangement direction of the first holes, a second shaped pattern in which a plurality of second holes are arranged and of which a width is periodically changed along an arrangement direction of the second holes, and slits which are formed along the arrangement direction of the first holes and separate the first shaped pattern and the second shaped pattern.

摘要翻译： 根据一个实施例，提供了一种第一成形图案，其中布置多个第一孔并且沿着第一孔的排列方向周期性地改变宽度，第二成形图案中多个第二孔是 沿着第二孔的排列方向周期性地改变宽度，沿着第一孔的排列方向形成并分离第一成形图案和第二成形图案的狭缝。

公开(公告)号：US20120241834A1

公开(公告)日：2012-09-27

申请号：US13234052

申请日：2011-09-15

申请人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Ryota Aburada ,  Chikaaki Kodama

发明人： Fumiharu Nakajima ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Ryota Aburada ,  Chikaaki Kodama

IPC分类号： H01L27/088 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/768 ,  H01L21/76816 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

摘要： According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(λ/NA) or less when an exposure wavelength of an exposure device is λ, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

摘要翻译： 根据一个实施例，半导体器件包括从元件形成区域延伸到绘图区域并且与元件形成区域中的半导体元件连接并且与绘图区域中的触点连接的互连。 基于在牺牲层的侧表面上匹配第n个（其中n是1或更大的整数）的第一侧壁膜的图案的第（n + 1）第二侧壁膜的图案形成互连。 当曝光装置的曝光波长为λ时，在元件形成区域中匹配互连的互连宽度的第一尺寸和元件形成区域中的互连间隔为（k1 / 2n）×（λ/ NA）或更小，透镜的数值孔径 的曝光装置为NA，处理参数为k1。 在绘图区域中匹配互连间隔的第二维大于第一维度。

公开(公告)号：US20100241261A1

公开(公告)日：2010-09-23

申请号：US12705640

申请日：2010-02-15

申请人： Takafumi TAGUCHI ,  Toshiya Kotani ,  Michiya Takimoto ,  Fumiharu Nakajima ,  Ryota Aburada ,  Hiromitsu Mashita ,  Katsumi Iyanagi ,  Chikaaki Kodama

发明人： Takafumi TAGUCHI ,  Toshiya Kotani ,  Michiya Takimoto ,  Fumiharu Nakajima ,  Ryota Aburada ,  Hiromitsu Mashita ,  Katsumi Iyanagi ,  Chikaaki Kodama

IPC分类号： G05B13/04 ,  G06F17/50 ,  G06F19/00

CPC分类号： G03F1/36

摘要： Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.

摘要翻译： 基于在处理条件下设置的多个处理参数进行OPC处理的设计布局数据执行模式形成模拟。 根据模拟结果提取的风险点计算过程条件的最差条件。 改变设计布局数据或OPC处理，使得当在最坏条件下基于改变的设计布局数据形成图案时，或者改变的OPC处理多个风险点或图案的风险点的风险程度 小于模拟结果。

公开(公告)号：US20100038795A1

公开(公告)日：2010-02-18

申请号：US12542540

申请日：2009-08-17

申请人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

发明人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

摘要翻译： 根据实施例的制造半导体器件的方法包括在基底层上形成具有恒定线宽度和第二图案的线性部分的第一图案，第二图案包括靠近第一图案的线性部分的部分和部分离开 从第一图案的直线部分和独立于第一图案构成闭环形状，或者处于连接到第一图案的状态，并且在第二图案的部分处远离线形部分进行闭环切割 第一种模式

公开(公告)号：US09268208B2

公开(公告)日：2016-02-23

申请号：US13421688

申请日：2012-03-15

申请人： Ryota Aburada ,  Hiromitsu Mashita ,  Taiga Uno ,  Masahiro Miyairi ,  Toshiya Kotani

发明人： Ryota Aburada ,  Hiromitsu Mashita ,  Taiga Uno ,  Masahiro Miyairi ,  Toshiya Kotani

IPC分类号： G03B27/42 ,  G03B27/54 ,  G03B27/68 ,  G03F1/36 ,  G03F7/20 ,  G03F1/70

CPC分类号： G03F1/36 ,  G03F1/22 ,  G03F1/70 ,  G03F7/70441 ,  G03F7/70941

摘要： One embodiment includes: a step of evaluating an amount of flare occurring through a mask at EUV exposure; a step of providing a dummy mask pattern on the mask based on the evaluated result of the amount of flare; and a step of executing a flare correction and an optical proximity correction on a layout pattern. The layout pattern is provided by the EUV exposure through the mask with the dummy mask pattern.

摘要翻译： 一个实施例包括：评估在EUV暴露下通过掩模发生的耀斑的量的步骤; 基于闪光量的评价结果​​，在掩模上设置虚拟掩模图案的步骤; 以及在布局图案上执行闪光校正和光学邻近校正的步骤。 布局图案由通过掩模的EUV曝光与伪掩模图案提供。

公开(公告)号：US08183148B2

公开(公告)日：2012-05-22

申请号：US12542540

申请日：2009-08-17

申请人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

发明人： Ryota Aburada ,  Hiromitsu Mashita ,  Toshiya Kotani ,  Chikaaki Kodama

IPC分类号： H01L21/4763

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

摘要翻译： 根据实施例的制造半导体器件的方法包括在基底层上形成具有恒定线宽度和第二图案的线性部分的第一图案，第二图案包括靠近第一图案的线性部分的部分和部分离开 从第一图案的直线部分和独立于第一图案构成闭环形状，或者处于连接到第一图案的状态，并且在第二图案的部分处远离线形部分进行闭环切割 第一种模式

公开(公告)号：US08336005B2

公开(公告)日：2012-12-18

申请号：US13050864

申请日：2011-03-17

申请人： Takafumi Taguchi ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Fumiharu Nakajima ,  Ryota Aburada ,  Chikaaki Kodama

发明人： Takafumi Taguchi ,  Toshiya Kotani ,  Hiromitsu Mashita ,  Fumiharu Nakajima ,  Ryota Aburada ,  Chikaaki Kodama

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position.

摘要翻译： 根据一个实施例的图案尺寸计算方法计算当在形成在基板上的电路图案的上层中处理电路图案时用作掩模的掩模构件的锥形形状。 该方法基于锥形形状从电路图案上的形状预测位置计算面向掩模构件的打开角度。 该方法根据在形状预测位置处形成的打开角度来计算电路图案的尺寸。

公开(公告)号：US08266552B2

公开(公告)日：2012-09-11

申请号：US12705640

申请日：2010-02-15

申请人： Takafumi Taguchi ,  Toshiya Kotani ,  Michiya Takimoto ,  Fumiharu Nakajima ,  Ryota Aburada ,  Hiromitsu Mashita ,  Katsumi Iyanagi ,  Chikaaki Kodama

发明人： Takafumi Taguchi ,  Toshiya Kotani ,  Michiya Takimoto ,  Fumiharu Nakajima ,  Ryota Aburada ,  Hiromitsu Mashita ,  Katsumi Iyanagi ,  Chikaaki Kodama

IPC分类号： G06F17/50 ,  G06F19/00 ,  G05B13/04

CPC分类号： G03F1/36

摘要： Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.

摘要翻译： 基于在处理条件下设置的多个处理参数进行OPC处理的设计布局数据来执行模式形成模拟。 根据模拟结果提取的风险点计算过程条件的最差条件。 改变设计布局数据或OPC处理，使得当在最坏条件下基于改变的设计布局数据形成图案时，或者改变的OPC处理多个风险点或图案的风险点的风险程度 小于模拟结果。

公开(公告)号：US20110065030A1

公开(公告)日：2011-03-17

申请号：US12880507

申请日：2010-09-13

申请人： Toshiya KOTANI ,  Fumiharu Nakajima ,  Ryota Aburada ,  Takafumi Taguchi ,  Hiromitsu Mashita ,  Michiya Takimoto ,  Chikaaki Kodama

发明人： Toshiya KOTANI ,  Fumiharu Nakajima ,  Ryota Aburada ,  Takafumi Taguchi ,  Hiromitsu Mashita ,  Michiya Takimoto ,  Chikaaki Kodama

IPC分类号： G03F7/20 ,  G06F17/50

CPC分类号： G06F17/5009 ,  G03F1/68 ,  G03F7/70425

摘要： According to one embodiment, a mask pattern determining method includes a mask-pattern dimension variation amount of a first photomask is derived. Moreover, a correspondence relationship between a target dimension value of an on-substrate test pattern formed by using a second photomask and a dimension allowable variation amount of a mask pattern formed on the second photomask is derived. Then, it is determined whether pattern formation is possible with a pattern dimension that needs to be formed when performing the pattern formation on a substrate by using the first photomask based on the mask-pattern dimension variation amount and the correspondence relationship.

摘要翻译： 根据一个实施例，掩模图案确定方法包括导出第一光掩模的掩模图案尺寸变化量。 此外，导出通过使用第二光掩模形成的基板上测试图案的目标尺寸值与形成在第二光掩模上的掩模图案的尺寸允许变化量之间的对应关系。 然后，基于掩模图案尺寸变化量和对应关系，通过使用第一光掩模在基板上进行图案形成时，确定是否可以形成图案尺寸。

公开(公告)号：US20100072454A1

公开(公告)日：2010-03-25

申请号：US12500208

申请日：2009-07-09

申请人： Ryota Aburada ,  Satoshi Tanaka

发明人： Ryota Aburada ,  Satoshi Tanaka

IPC分类号： H01L45/00 ,  G03B27/32

CPC分类号： G03B27/32

摘要： An exposure method includes an exposure process for exposing a substrate through a halftone mask with quadrupole illumination to form plural columnar portions that are disposed into a matrix shape in a first direction and a second direction orthogonal to the first direction. The halftone mask includes a first pattern that is extended in the first direction and disposed at predetermined pitches in the second direction; and a second pattern that is extended in the second direction and disposed at predetermined pitches in the first direction such that an intersection portion intersecting the first pattern is formed. The pitches and widths of the patterns on the halftone mask are configured such that zero-order diffracted light intensity and first-order diffracted light intensity, diffracted by the halftone mask, are substantially matched with each other and such that a first-order diffracted light phase is inverted with respect to a zero-order diffracted light phase.

摘要翻译： 曝光方法包括曝光工艺，用于通过具有四极照明的半色调掩模曝光衬底以形成在与第一方向正交的第一方向和第二方向上设置成矩阵形状的多个柱状部分。 半色调掩模包括沿第一方向延伸并以第二方向以预定间距布置的第一图案; 以及第二图案，其沿第二方向延伸并且以第一方向以预定间距设置，使得形成与第一图案相交的交叉部分。 半色调掩模上的图案的间距和宽度被配置为使得被半色调掩模衍射的零级衍射光强度和一级衍射光强度基本上彼此匹配，并且使得一级衍射光 相位相对于零级衍射光相反相。