公开(公告)号：US10825509B2

公开(公告)日：2020-11-03

申请号：US16146932

申请日：2018-09-28

Applicant: Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G11C11/00 ,  G11C11/419 ,  G11C27/02 ,  G11C7/10 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418

Abstract: A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.

公开(公告)号：US20200091414A1

公开(公告)日：2020-03-19

申请号：US16130912

申请日：2018-09-13

Applicant: Huichu Liu ,  Sasikanth Manipatruni ,  Daniel Morris ,  Kaushik Vaidyanathan ,  Tanay Karnik ,  Ian Young

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Daniel Morris ,  Kaushik Vaidyanathan ,  Tanay Karnik ,  Ian Young

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  G11C11/16 ,  G11C11/18

Abstract: An apparatus is provided which comprises a full adder including magnetoelectric material and spin orbit material. In some embodiments, the adder includes: a 3-bit carry generation structure and a multi-bit sum generation structure coupled to the 3-bit carry generation structure. In some embodiments, the 3-bit carry generation structure includes at least three cells comprising magnetoelectric material and spin orbit material, wherein the 3-bit carry generation structure is to perform a minority logic operation on first, second, and third inputs to generate a carry output. In some embodiments, the multi-bit sum generation structure includes at least four cells comprising magnetoelectric material and spin orbit material, wherein the multi-bit sum generation structure is to perform a minority logic operation on the first, second, and third inputs and the carry output to generate a sum output.

公开(公告)号：US20190057050A1

公开(公告)日：2019-02-21

申请号：US16160952

申请日：2018-10-15

Applicant: Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

IPC: G06F13/16 ,  G06F13/28

Abstract: Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

公开(公告)号：US09711284B2

公开(公告)日：2017-07-18

申请号：US13711531

申请日：2012-12-11

Applicant: Brian S. Doyle ,  Sasikanth Manipatruni ,  Shawna M. Liff ,  Vivek K. Singh

Inventor： Brian S. Doyle ,  Sasikanth Manipatruni ,  Shawna M. Liff ,  Vivek K. Singh

IPC: H01G4/16 ,  H01G4/30 ,  H01G4/28 ,  H01L29/06 ,  H01G4/008 ,  B82Y10/00 ,  H01L49/02 ,  D03D1/00 ,  H01L29/775

CPC classification number: H01G4/008 ,  B82Y10/00 ,  D03D1/0088 ,  D10B2401/18 ,  H01G4/28 ,  H01L28/60 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/775 ,  Y02E60/13

Abstract: A charge storage fiber is described. In an embodiment, the charge storage fiber includes a flexible electrically conducting fiber, a dielectric coating on the flexible electrically conducting fiber, and a metal coating on the dielectric coating. In an embodiment, the charge storage fiber is attached to a textile-based product.

公开(公告)号：US08988109B2

公开(公告)日：2015-03-24

申请号：US13678877

申请日：2012-11-16

Applicant: Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H03K17/16 ,  H03K19/16

CPC classification number: H03K19/16 ,  G11C11/16 ,  G11C11/161 ,  H01F10/3268 ,  H03K17/80

Abstract: High speed precessionally switched magnetic logic devices and architectures are described. In a first example, a magnetic logic device includes an input electrode having a first nanomagnet and an output electrode having a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. In a second example, a magnetic logic device includes an input electrode having an in-plane nanomagnet and an output electrode having a perpendicular magnetic anisotropy (PMA) magnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes.

Abstract translation: 描述了高速开关磁逻辑器件和架构。 在第一示例中，磁逻辑器件包括具有第一纳米磁体的输入电极和具有第二纳米磁体的输出电极。 第二纳米磁体的自旋与第一纳米磁体的自旋不共线。 沟道区域和对应的接地电极设置在输入和输出电极之间。 在第二示例中，磁逻辑器件包括具有面内纳米磁体的输入电极和具有垂直磁各向异性（PMA）磁体的输出电极。 沟道区域和对应的接地电极设置在输入和输出电极之间。

公开(公告)号：US20140292429A1

公开(公告)日：2014-10-02

申请号：US13994714

申请日：2013-03-28

Applicant: Sasikanth Manipatruni ,  Raseong Kim ,  Rajashree Baskaran ,  Rajeev K. Dokania ,  Ian A. Young

Inventor： Sasikanth Manipatruni ,  Raseong Kim ,  Rajashree Baskaran ,  Rajeev K. Dokania ,  Ian A. Young

IPC: B81B3/00 ,  H03B5/30 ,  B81C1/00

CPC classification number: H03B5/30 ,  H01L29/66795 ,  H01L29/7831 ,  H01L2924/13067 ,  H01L2924/13084

Abstract: An embodiment includes an oscillator comprising an amplifier formed on a substrate; a multiple gate resonant channel array, formed on the substrate, including: (a) transistors including fins, each of the fins having a channel between source and drain nodes, coupled to common source and drain contacts; and (b) common first and second tri-gates coupled to each of the fins and located between the source and drain contacts; wherein the fins mechanically resonate at a first frequency when one of the first and second tri-gates is periodically activated to produce periodic downward forces on the fins. Other embodiments include a non planar transistor with a channel between the source and drain nodes and a tri-gate on the fin; wherein the fin mechanically resonates when the first tri-gate is periodically activated to produce periodic downward forces on the fin. Other embodiments are described herein.

Abstract translation: 实施例包括：振荡器，包括形成在基板上的放大器; 形成在所述衬底上的多栅极共振沟道阵列包括：（a）包括鳍片的晶体管，每个鳍片在源极和漏极节点之间具有耦合到共源极和漏极触点的沟道; 和（b）共同的第一和第二三栅极，其耦合到每个散热片并且位于源极和漏极接触之间; 其中当第一和第二三门中的一个被周期性地激活以在翅片上产生周期性向下的力时，翅片以第一频率机械共振。 其他实施例包括在源极和漏极节点之间具有沟道的非平面晶体管和鳍上的三栅极; 其中当所述第一三栅极被周期性地激活以在所述散热片上产生周期性向下的力时，所述翅片机械谐振。 本文描述了其它实施例。

公开(公告)号：US20140173716A1

公开(公告)日：2014-06-19

申请号：US13717433

申请日：2012-12-17

Applicant: Sasikanth Manipatruni ,  Kelin J. Kuhn ,  Debendra Mallik ,  John C. Johnson

Inventor： Sasikanth Manipatruni ,  Kelin J. Kuhn ,  Debendra Mallik ,  John C. Johnson

IPC: G06F21/44

CPC classification number: G06F21/44 ,  G06F21/10 ,  G06F21/35

Abstract: Managing and accessing personal data is described. In one example, an apparatus has an application processor, a memory to store data, a receive and a transmit array coupled to the application processor to receive data to store in the memory and to transmit data stored in the memory through a wireless interface, and an inertial sensor to receive user commands to authorize the processor to receive and transmit data through the receive and transmit array.

Abstract translation: 描述管理和访问个人数据。 在一个示例中，设备具有应用处理器，用于存储数据的存储器，耦合到应用处理器的接收和发送阵列，以接收存储在存储器中的数据并通过无线接口传输存储在存储器中的数据，以及 惯性传感器，用于接收用户命令，以授权处理器通过接收和发送阵列接收和发送数据。

公开(公告)号：US20140170919A1

公开(公告)日：2014-06-19

申请号：US13714990

申请日：2012-12-14

Applicant: Sasikanth Manipatruni ,  Brian S. Doyle ,  Shawna M. Liff ,  Vivek K. Singh

Inventor： Sasikanth Manipatruni ,  Brian S. Doyle ,  Shawna M. Liff ,  Vivek K. Singh

IPC: D03D1/00 ,  H01B7/04 ,  D01D5/04 ,  B21C3/00 ,  D04H3/00 ,  D02G3/44

CPC classification number: D03D1/0088 ,  B21C23/08 ,  B21C37/042 ,  B21C37/047 ,  D01D5/00 ,  D01D5/34 ,  D02G3/441 ,  D04H1/4266 ,  D04H1/4382 ,  D04H3/00 ,  D10B2401/16 ,  D10B2401/18 ,  Y10T442/3057 ,  Y10T442/603

Abstract: Flexible electronically functional fibers are described that allow for the placement of electronic functionality in traditional fabrics. The fibers can be interwoven with natural fibers to produce electrically functional fabrics and devices that can retain their original appearance.

Abstract translation: 描述了允许在传统织物中放置电子功能的柔性电子功能纤维。 纤维可与天然纤维交织以产生可保持其原始外观的电功能织物和装置。

公开(公告)号：US20140139265A1

公开(公告)日：2014-05-22

申请号：US13678877

申请日：2012-11-16

Applicant: Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H03K19/16

CPC classification number: H03K19/16 ,  G11C11/16 ,  G11C11/161 ,  H01F10/3268 ,  H03K17/80

Abstract: High speed precessionally switched magnetic logic devices and architectures are described. In a first example, a magnetic logic device includes an input electrode having a first nanomagnet and an output electrode having a second nanomagnet. The spins of the second nanomagnet are non-collinear with the spins of the first nanomagnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes. In a second example, a magnetic logic device includes an input electrode having an in-plane nanomagnet and an output electrode having a perpendicular magnetic anisotropy (PMA) magnet. A channel region and corresponding ground electrode are disposed between the input and output electrodes.

Abstract translation: 描述了高速开关磁逻辑器件和架构。 在第一示例中，磁逻辑器件包括具有第一纳米磁体的输入电极和具有第二纳米磁体的输出电极。 第二纳米磁体的自旋与第一纳米磁体的自旋不共线。 沟道区域和对应的接地电极设置在输入和输出电极之间。 在第二示例中，磁逻辑器件包括具有面内纳米磁体的输入电极和具有垂直磁各向异性（PMA）磁体的输出电极。 沟道区域和对应的接地电极设置在输入和输出电极之间。

公开(公告)号：US20130056623A1

公开(公告)日：2013-03-07

申请号：US13697866

申请日：2011-05-13

Applicant: Michal Lipson ,  Sasikanth Manipatruni ,  Long Chen ,  Kyle Preston

Inventor： Michal Lipson ,  Sasikanth Manipatruni ,  Long Chen ,  Kyle Preston

IPC: H01L31/105 ,  G01J1/04 ,  H01L31/18

CPC classification number: G02B6/29338 ,  G02B6/12007 ,  G02B6/136 ,  G02B6/29341 ,  G02B2006/12142 ,  G02F1/3133 ,  Y02P70/521

Abstract: An electro-optic modulator structure, a method for fabricating the electro-optic modulator structure, a method for operating an electro-optic modulator device that derives from the electro-optic modulator structure and a related communications apparatus that includes the electro-optic modulator structure all are directed towards effecting a comparatively low voltage operation of the electro-optic modulator device predicated upon consideration of optimal charge carrier injection efficiency characteristics of a PIN diode charge carrier injection based micro-ring electro-optic modulator structure as a function of applied bias voltage. To realize the foregoing result, at least in part, the PIN diode charge carrier injection based electro-optic modulator structure includes at least one of a p-doped region and an n-doped region that has a relatively high volume dopant concentration at a surface thereof.

Abstract translation: 电光调制器结构，用于制造电光调制器结构的方法，用于操作从电光调制器结构导出的电光调制器装置的方法和包括电光调制器结构的相关通信装置 所有这些都旨在实现电光调制器装置的相当低的电压操作，其基于考虑作为施加的偏置电压的基于PIN二极管电荷载流子注入的微环电光调制器结构的最佳电荷载流子注入效率特性 。 为了实现上述结果，至少部分地基于PIN二极管电荷载流子注入的电光调制器结构包括在表面上具有相对高的体积掺杂剂浓度的p掺杂区域和n掺杂区域中的至少一个 其中。