公开(公告)号：US08959008B2

公开(公告)日：2015-02-17

申请号：US13023559

申请日：2011-02-09

Applicant: Michael Claus Olsen ,  Jie Deng ,  Terence B. Hook ,  Madan Mohan Naga Nutakki

Inventor： Michael Claus Olsen ,  Jie Deng ,  Terence B. Hook ,  Madan Mohan Naga Nutakki

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5036

Abstract: Performing a transient analysis with a compact FET model that is predominantly intended for DC analysis, such as an IDDQ leakage model, to enable toggling logic states in sequential logic circuits that cannot otherwise be examined in a DC analysis. An embodiment enables examining the DC or AC conditions of any logic state of any logic circuit in a DC or AC analysis, and additionally, it eliminates a potentially long execution time of a transient analysis with a DC model. Further solved is the present need to run two simulations and to maintain two netlists in order to overcome being unable to toggle certain logic states in the DC analysis. The invention achieves the aforementioned in a single simulation with a single netlist that calculates the DC operating circuit conditions with a model A on the fly at predetermined times or in certain logic states, during a transient analysis with a model B.

Abstract translation: 使用主要用于直流分析（例如IDDQ泄漏模型）的紧凑型FET模型进行瞬态分析，以便能够在不能在DC分析中检查的顺序逻辑电路中切换逻辑状态。 一个实施例能够检查DC或AC分析中任何逻辑电路的任何逻辑状态的DC或AC条件，此外，它消除了具有DC模型的瞬态分析的潜在长的执行时间。 进一步的解决是目前需要运行两个模拟并且维护两个网表，以克服在DC分析中不能切换某些逻辑状态。 本发明在具有单个网表的单个模拟中实现上述，在单个网表中，在模型B的瞬态分析期间，在预定时间或在某些逻辑状态下，用模型A计算直流运行电路条件。

公开(公告)号：US20130221987A1

公开(公告)日：2013-08-29

申请号：US13407822

申请日：2012-02-29

Applicant: Hayden C. Cranford, JR. ,  Terence B. Hook

Inventor： Hayden C. Cranford, JR. ,  Terence B. Hook

IPC: G01R29/26

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C2029/0409 ,  G11C2029/5002

Abstract: A monitoring circuit and method, wherein a voltage waveform having a linear falling edge is applied to a first node of at least one test memory cell (e.g., a plurality of test memory cells connected in parallel). The input voltage at the first node is captured when the output voltage at a second node of the test memory cell(s) rises above a high reference voltage during the falling edge. Then, a difference is determined between the input voltage as captured and either (1) the output voltage at the second node, as captured when the input voltage at the first node falls below the first reference voltage during the falling edge, or (2) a low reference voltage. This difference is proportional to the static noise margin (SNM) of the test memory cell(s) such that any changes in the difference noted with repeated monitoring are indicative of corresponding changes in the SNM.

Abstract translation: 一种监视电路和方法，其中具有线性下降沿的电压波形被施加到至少一个测试存储器单元（例如，并联连接的多个测试存储单元）的第一节点。 当在下降沿期间，当测试存储单元的第二个节点处的输出电压上升到高于参考电压时，捕获第一节点处的输入电压。 然后，在捕获的输入电压和（1）第二节点处的输出电压之间确定差异，如在第一节点处的输入电压在下降沿期间低于第一参考电压时捕获的，或者（2） 低参考电压。 该差异与测试存储器单元的静态噪声容限（SNM）成比例，使得通过重复监测指出的差异中的任何变化表示SNM的相应变化。

公开(公告)号：US20130134545A1

公开(公告)日：2013-05-30

申请号：US13306621

申请日：2011-11-29

Applicant: Terence B. Hook ,  Vijay Narayanan ,  Jay M. Shah ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Helen H. Wang ,  Chendong Zhu

Inventor： Terence B. Hook ,  Vijay Narayanan ,  Jay M. Shah ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Helen H. Wang ,  Chendong Zhu

IPC: H01L29/06 ,  H01L21/28

CPC classification number: H01L21/28247 ,  H01L21/28123 ,  H01L21/76224

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：半导体衬底，包括：高K电介质区域; 阻挡区域，其设置成抵抗高K电介质区域的至少一个表面，并且适于响应于暴露于氧气而形成氧化层; 以及设置在阻挡区域上的富氧区域，使得阻挡区域介于富氧区域和高K电介质区域之间。

公开(公告)号：US20120214280A1

公开(公告)日：2012-08-23

申请号：US13460871

申请日：2012-05-01

Applicant: Douglas D. COOLBAUGH ,  Ebenezer E. ESHUN ,  Terence B. HOOK ,  Robert M. RASSEL ,  Edmund J. SPROGIS ,  Anthony K. STAMPER ,  William J. MURPHY

Inventor： Douglas D. COOLBAUGH ,  Ebenezer E. ESHUN ,  Terence B. HOOK ,  Robert M. RASSEL ,  Edmund J. SPROGIS ,  Anthony K. STAMPER ,  William J. MURPHY

IPC: H01L21/50

CPC classification number: H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

Abstract translation: 提供带散热片的电阻。 散热器包括具有导热性高的金属或其它热导体的导电路径。 为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。 因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。 除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

公开(公告)号：US20120203532A1

公开(公告)日：2012-08-09

申请号：US13023559

申请日：2011-02-09

Applicant: Michael Claus Olsen ,  Jie Deng ,  Terence B. Hook ,  Madan Mohan Naga Nutakki

Inventor： Michael Claus Olsen ,  Jie Deng ,  Terence B. Hook ,  Madan Mohan Naga Nutakki

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5036

Abstract: Performing a transient analysis with a compact FET model that is predominantly intended for DC analysis, such as an IDDQ leakage model, to enable toggling logic states in sequential logic circuits that cannot otherwise be examined in a DC analysis. An embodiment enables examining the DC or AC conditions of any logic state of any logic circuit in a DC or AC analysis, and additionally, it eliminates a potentially long execution time of a transient analysis with a DC model. Further solved is the present need to run two simulations and to maintain two netlists in order to overcome being unable to toggle certain logic states in the DC analysis. The invention achieves the aforementioned in a single simulation with a single netlist that calculates the DC operating circuit conditions with a model A on the fly at predetermined times or in certain logic states, during a transient analysis with a model B.

Abstract translation: 使用主要用于直流分析（例如IDDQ泄漏模型）的紧凑型FET模型进行瞬态分析，以便能够在不能在DC分析中检查的顺序逻辑电路中切换逻辑状态。 一个实施例能够检查DC或AC分析中任何逻辑电路的任何逻辑状态的DC或AC条件，此外，它消除了具有DC模型的瞬态分析的潜在长的执行时间。 进一步的解决是目前需要运行两个模拟，并维护两个网表，以克服在DC分析中不能切换某些逻辑状态。 本发明在具有单个网表的单个模拟中实现上述，在单个网表中，在模型B的瞬态分析期间，在预定时间或在某些逻辑状态下，用模型A计算直流运行电路条件。

公开(公告)号：US07928513B2

公开(公告)日：2011-04-19

申请号：US12317310

申请日：2008-12-22

Applicant: Terence B. Hook ,  Anda C. Mocuta ,  Jeffrey W. Sleight ,  Anthony K. Stamper

Inventor： Terence B. Hook ,  Anda C. Mocuta ,  Jeffrey W. Sleight ,  Anthony K. Stamper

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

Abstract: A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

Abstract translation: 芯片可以包括CMOS结构，其具有设置在半导体衬底的第一区域中的体器件，其与衬底的下面的体区域导电连通，第一区域和体区具有第一晶体取向。 SOI器件设置在绝缘体上半导体（“SOI”）层中，其通过掩埋电介质层与衬底的本体区域分离，SOI层具有与第一晶体取向不同的晶体取向。 在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，体器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与本体器件的栅极导体导通的栅极导体时，除了存在与体区域反向偏置导电连通的二极管之外，SOI器件可能发生充电损坏。 当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

公开(公告)号：US07572650B2

公开(公告)日：2009-08-11

申请号：US11550853

申请日：2006-10-19

Applicant: Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

Inventor： Jonathan D. Chapple-Sokol ,  Terence B. Hook ,  Baozhen Li ,  Thomas L. McDevitt ,  Christopher A. Ponsolle ,  Bette B. Reuter ,  Timothy D. Sullivan ,  Jeffrey S. Zimmerman

IPC: H01L21/00

CPC classification number: H01L21/7684 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

Abstract translation: 用于抑制半导体加工中的局部金属沉淀形成（LMPF）的方法和结构。 对于暴露于制造环境并且电耦合到N区域的每个金属线，至少一个P +区形成为电耦合到相同的金属线。 结果，几乎没有多余的电子可用于与金属离子结合以在金属线上形成局部金属沉淀。 可以在金属线周围形成监测斜坡端子并与金属线电断开。 通过向金属线和监视斜坡端子施加电压差并测量流过金属线和监视斜坡端子的所得电流，可以确定在金属线处是否形成了局部金属沉淀物。

公开(公告)号：US07516426B2

公开(公告)日：2009-04-07

申请号：US11561537

申请日：2006-11-20

Applicant: Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

Inventor： Terence B. Hook ,  Jeffrey B. Johnson ,  Yoo-Mi Lee

IPC: G06F17/50

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L27/0207

Abstract: Methods of improving operational parameters between at least a pair of matched transistors, and a set of transistors, are disclosed. One embodiment of a method includes a method of improving at least one of a threshold voltage (Vt) mismatch and current drive between at least a pair of matched transistors for analog applications, the method comprising: forming at least a pair of transistors, each with a gate having a plurality of connected fingers; and optimizing a total length of a channel under the plurality of fingers to attain at least one of: a) a reduced threshold voltage mismatch between the at least pair of transistors, and b) increased current drive for a given threshold voltage mismatch, between the at least pair of transistors, each finger having a length less than an overall length of the channel.

Abstract translation: 公开了改善至少一对匹配晶体管之间的操作参数的方法和一组晶体管。 方法的一个实施例包括一种改进用于模拟应用的至少一对匹配晶体管之间的阈值电压（Vt）失配和电流驱动中的至少一个的方法，所述方法包括：形成至少一对晶体管，每个晶体管具有 具有多个连接的手指的门; 以及优化所述多个指状物下的通道的总长度以达到以下至少一个：a）所述至少一对晶体管之间的阈值电压失配降低，以及b）对于给定阈值电压失配的增加的电流驱动， 至少一对晶体管，每个手指的长度小于通道的总长度。

公开(公告)号：US07302376B2

公开(公告)日：2007-11-27

申请号：US10248853

申请日：2003-02-25

Applicant: Eric Adler ,  Serge Biesemans ,  Micah S. Galland ,  Terence B. Hook ,  Judith H. McCullen ,  Eric S. Phipps ,  James A. Slinkman

Inventor： Eric Adler ,  Serge Biesemans ,  Micah S. Galland ,  Terence B. Hook ,  Judith H. McCullen ,  Eric S. Phipps ,  James A. Slinkman

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G06F17/5036 ,  G06F17/5068

Abstract: A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

Abstract translation: 一种用于校正由相邻结构施加的变量的给定感兴趣结构的软件模型的方法。 首先确定相邻结构施加的变量的空间范围。 然后为空间范围分配一个值，该空间范围随着从相邻结构到给定结构的距离的函数而变化。 最后，将该值附加到给定结构的模型中。

公开(公告)号：US07166904B2

公开(公告)日：2007-01-23

申请号：US10708023

申请日：2004-02-03

Applicant: Jason P. Gill ,  Terence B. Hook ,  Randy W. Mann ,  William J. Murphy ,  William R. Tonti ,  Steven H. Voldman

Inventor： Jason P. Gill ,  Terence B. Hook ,  Randy W. Mann ,  William J. Murphy ,  William R. Tonti ,  Steven H. Voldman

IPC: H01L29/00

CPC classification number: H01L27/11 ,  H01L27/0288 ,  H01L27/0802 ,  H01L27/1112 ,  H01L27/1203 ,  H01L29/7304 ,  H01L29/7378 ,  H01L29/7391 ,  H01L29/78 ,  Y10S257/903 ,  Y10S257/904

Abstract: A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.

Abstract translation: 一种用于形成具有优异的ESD保护特性的半导体器件的方法和系统。 电阻材料层设置在触头螺柱上下表面中的至少一个上的接触孔内。 在优选实施例中，积分电阻器的电阻值介于约1欧姆至约10欧姆之间，或10欧姆至100欧姆之间。 电阻层的实施例包括溅射硅材料，隧道氧化物，隧道氮化物，硅注入氧化物，注入硅的氮化物或非晶多晶硅。 本发明的实施例包括SRAM，双极晶体管，SOI横向二极管，MOSFET和SiGe晶体管。