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    Clock signal circuitry for multi-channel data signaling
    1.
    发明授权
    Clock signal circuitry for multi-channel data signaling 有权
    用于多通道数据信号的时钟信号电路

    公开(公告)号：US07812659B1

    公开(公告)日：2010-10-12

    申请号：US11432420

    申请日：2006-05-10

    申请人： Sergey Shumarayev ,  Rakesh H Patel ,  William W Bereza ,  Tim Tri Hoang ,  Thungoc Tran

    发明人： Sergey Shumarayev ,  Rakesh H Patel ,  William W Bereza ,  Tim Tri Hoang ,  Thungoc Tran

    IPC分类号： G06F1/04 ,  H04L7/00

    CPC分类号： H03L7/22 ,  G06F1/06

    摘要： A programmable logic device (“PLD”) or the like has a plurality of data transmitter channels. Certain circuitry is shared by the channels. The shared circuitry includes at least one phase-locked loop (“PLL”) circuit for producing a primary clock signal, and global frequency divider circuitry for producing at least one global secondary clock signal based on the primary signal. The primary and global secondary signal(s) are distributed to the channels. Each of the channels includes local frequency divider circuitry for producing at least one local secondary clock signal based on the primary signal. Each channel also includes selection circuitry for selecting either the global or local secondary signal(s) for use by clock utilization circuitry of the channel. The clock utilization circuitry may include serializer circuitry for converting data from parallel to serial form.

    摘要翻译： 可编程逻辑器件（“PLD”）等具有多个数据发送器通道。 某些电路由通道共享。 共享电路包括用于产生主时钟信号的至少一个锁相环（“PLL”）电路和用于基于主信号产生至少一个全局辅助时钟信号的全局分频器电路。 主要和全局辅助信号被分配到信道。 每个通道包括本地分频器电路，用于基于主信号产生至少一个本地辅助时钟信号。 每个通道还包括选择电路，用于选择由信道的时钟利用电路使用的全局或局部辅助信号。 时钟利用电路可以包括用于将数据从并行转换为串行形式的串行化器电路。

    Memory circuitry for programmable logic integrated circuit devices
    4.
    发明授权
    Memory circuitry for programmable logic integrated circuit devices 有权

    公开(公告)号：US06556502B2

    公开(公告)日：2003-04-29

    申请号：US10134886

    申请日：2002-04-26

    申请人： Tony Ngai ,  Nitin Prasad ,  Thungoc Tran

    发明人： Tony Ngai ,  Nitin Prasad ,  Thungoc Tran

    IPC分类号： G11C800

    CPC分类号： H03K19/1776 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/005

    摘要： A programmable logic device includes, in addition to the usual regions of programmable logic and the programmable interconnect, at least one region of memory which has multiple independently usable write and/or read ports (e.g., two write ports and two read ports). Every memory cell in the memory region is accessible from any of these ports. This enables the memory region to be used to provide either one relatively large memory or two somewhat smaller memories, each occupying a fraction of the full memory. In the latter case, the two memories provided can have any of many different sizes relative to one another. Many different modes or combinations of modes of operating the memory region or parts of the memory region are possible.

    Programmable receiver equalization circuitry and methods
    5.
    发明授权
    Programmable receiver equalization circuitry and methods 有权
    可编程接收机均衡电路和方法

    公开(公告)号：US07697600B2

    公开(公告)日：2010-04-13

    申请号：US11182658

    申请日：2005-07-14

    申请人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

    发明人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03885 ,  H04B3/04 ,  H04L25/03019

    摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.

    摘要翻译： 通过传输介质传输的数据信号遭受由传输介质引起的衰减。 可以提供均衡电路以补偿由传输介质引起的衰减。 均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。 每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。 每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。

    Clock circuitry for programmable logic devices
    7.
    发明授权
    Clock circuitry for programmable logic devices 有权
    可编程逻辑器件的时钟电路

    公开(公告)号：US07276936B1

    公开(公告)日：2007-10-02

    申请号：US11239702

    申请日：2005-09-29

    申请人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  In Whan Kim ,  Thungoc Tran

    发明人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  In Whan Kim ,  Thungoc Tran

    IPC分类号： H03K19/00

    CPC分类号： H03K19/1774 ,  H03K19/17744

    摘要： A programmable logic device includes high-speed serial interface (“HSSI”) circuitry that employs one or more clock signals. In addition to use of these clock signals in the HSSI circuitry, circuitry is provided for allowing at least one of these signals to be distributed throughout the PLD core circuitry, e.g., for use as an additional clock signal in the PLD core. Clock distribution is preferably done in a low-skew way.

    摘要翻译： 可编程逻辑器件包括采用一个或多个时钟信号的高速串行接口（“HSSI”）电路。 除了在HSSI电路中使用这些时钟信号之外，提供电路以允许这些信号中的至少一个分布在整个PLD核心电路中，例如用作PLD核心中的附加时钟信号。 时钟分布优选以低偏斜方式进行。

    Programmable receiver equalization circuitry and methods
    8.
    发明申请
    Programmable receiver equalization circuitry and methods 有权
    可编程接收机均衡电路和方法

    公开(公告)号：US20070014344A1

    公开(公告)日：2007-01-18

    申请号：US11182658

    申请日：2005-07-14

    申请人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

    发明人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

    IPC分类号： H03H7/30

    CPC分类号： H04L25/03885 ,  H04B3/04 ,  H04L25/03019

    摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.

    摘要翻译： 通过传输介质传输的数据信号遭受由传输介质引起的衰减。 可以提供均衡电路以补偿由传输介质引起的衰减。 均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。 每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。 每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。

    Multi-channel communication circuitry for programmable logic device integrated circuits and the like
    10.
    发明申请
    Multi-channel communication circuitry for programmable logic device integrated circuits and the like 有权
    用于可编程逻辑器件集成电路等的多通道通信电路

    公开(公告)号：US20070058618A1

    公开(公告)日：2007-03-15

    申请号：US11288810

    申请日：2005-11-28

    申请人： Thungoc Tran ,  Sergey Shumarayev ,  Tim Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

    发明人： Thungoc Tran ,  Sergey Shumarayev ,  Tim Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

    IPC分类号： H04L12/50

    CPC分类号： H03K19/17736 ,  H03K19/17744

    摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.

    摘要翻译： 诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。 提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作 一起，八个渠道在一起等）。 共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。 电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以促进诸如电路设计和验证的事情。