公开(公告)号：US11373871B2

公开(公告)日：2022-06-28

申请号：US16577353

申请日：2019-09-20

Applicant: APPLIED MATERIALS, INC.

Inventor： Benjamin Colombeau ,  Wolfgang R. Aderhold ,  Andy Lo ,  Yi-Chiau Huang

IPC: H01L21/225 ,  H01L29/66 ,  H01L21/324 ,  H01L21/02

Abstract: Methods and apparatus for forming doped material layers in semiconductor devices using an integrated selective monolayer doping (SMLD) process. A concentration of dopant is deposited on a material layer using the SMLD process and the concentration of dopant is then annealed to diffuse the concentration of dopant into the material layer. The SMLD process conforms the concentration of dopant to a surface of the material layer and may be performed in a single CVD chamber. The SMLD process may also be repeated to further alter the diffusion parameters of the dopant into the material layer. The SMLD process is compatible with p-type dopant species and n-type dopant species.

公开(公告)号：US20220123123A1

公开(公告)日：2022-04-21

申请号：US17498098

申请日：2021-10-11

Applicant: Applied Materials, Inc.

Inventor： Myungsun Kim ,  Andy Lo ,  Eric Davey ,  Michael Stolfi ,  Benjamin Colombeau

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/66

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise an oxide layer and a semiconductor material layer between source regions and drain regions of the device. The method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer. An alternative method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by a surface treatment, and then radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer.

公开(公告)号：US11923441B2

公开(公告)日：2024-03-05

申请号：US17888894

申请日：2022-08-16

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/455 ,  C23C16/56 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/6681 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/45536 ,  C23C16/56 ,  C30B29/06 ,  C30B29/52 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L29/42392 ,  H01L29/6653

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US11195923B2

公开(公告)日：2021-12-07

申请号：US16678526

申请日：2019-11-08

Applicant: Applied Materials, Inc.

Inventor： Gaurav Thareja ,  Xuebin Li ,  Abhishek Dube ,  Yi-Chiau Huang ,  Tushar Vidyadhar Mandrekar ,  Andy Lo ,  Patricia M. Liu ,  Sanjay Natarajan ,  Saurabh Chopra

IPC: H01L21/44 ,  H01L29/40 ,  H01L29/417 ,  H01L21/02 ,  H01L29/08 ,  H01L21/67 ,  H01L29/66 ,  H01L21/285 ,  H01L29/45

Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.

公开(公告)号：US12243941B2

公开(公告)日：2025-03-04

申请号：US17386711

申请日：2021-07-28

Applicant: Applied Materials, Inc.

Inventor： Myungsun Kim ,  Michael Stolfi ,  Benjamin Colombeau ,  Andy Lo

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/15 ,  H01L29/16 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US20220399457A1

公开(公告)日：2022-12-15

申请号：US17888894

申请日：2022-08-16

Applicant: Applied Materials, Inc.

Inventor： Steven C.H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  C30B29/06 ,  C30B29/52 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/56 ,  C23C16/455

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US11450759B2

公开(公告)日：2022-09-20

申请号：US17037941

申请日：2020-09-30

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  C30B29/06 ,  C30B29/52 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/56 ,  C23C16/455

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US20220037529A1

公开(公告)日：2022-02-03

申请号：US17386711

申请日：2021-07-28

Applicant: Applied Materials, Inc.

Inventor： Myungsun Kim ,  Michael Stolfi ,  Benjamin Colombeau ,  Andy Lo

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/15 ,  H01L21/8234 ,  H01L21/02

Abstract: Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US11152479B2

公开(公告)日：2021-10-19

申请号：US16773848

申请日：2020-01-27

Applicant: Applied Materials, Inc.

Inventor： Gaurav Thareja ,  Xuebin Li ,  Abhishek Dube ,  Yi-Chiau Huang ,  Andy Lo ,  Patricia M. Liu ,  Sanjay Natarajan ,  Saurabh Chopra

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78 ,  H01L29/417

Abstract: The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. Embodiments of the present disclosure enable formation of a source/drain contact with reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.

公开(公告)号：US20210104617A1

公开(公告)日：2021-04-08

申请号：US17037941

申请日：2020-09-30

Applicant: Applied Materials, Inc.

Inventor： Steven C.H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  C30B29/06 ,  C30B29/52 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/455 ,  C23C16/56

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.