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    UV-ASSISTED REACTIVE ION ETCH FOR COPPER
    4.
    发明申请
    UV-ASSISTED REACTIVE ION ETCH FOR COPPER 审中-公开
    紫外辅助反应离子蚀刻铜

    公开(公告)号：US20140262755A1

    公开(公告)日：2014-09-18

    申请号：US14201892

    申请日：2014-03-09

    Applicant: Applied Materials, Inc.

    Inventor： Subhash Deshmukh ,  Jingjing Liu ,  He Ren

    IPC: H01J37/32 ,  C23F4/00

    CPC classification number: H01J37/32155 ,  C23F4/00 ,  H01J37/32128 ,  H01J37/32146 ,  H01J37/32431 ,  H01J37/32724 ,  H01J2237/334 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/02068 ,  H01L21/3065 ,  H01L21/67115

    Abstract: In some embodiments, a plasma etching apparatus is provided for etching copper that includes (1) a chamber body having a process chamber adapted to receive a substrate; (2) an RF source coupled to an RF electrode; (3) a pedestal located in the processing chamber and adapted to support a substrate; and (4) a UV source configured to delivery UV light to the processing chamber during at least a portion of an etch process performed within the plasma etching apparatus. Numerous other aspects are provided.

    Abstract translation: 在一些实施例中，提供了用于蚀刻铜的等离子体蚀刻装置，其包括（1）具有适于接纳基板的处理室的室主体; （2）耦合到RF电极的RF源; （3）位于处理室中并适于支撑基板的基座; 以及（4）UV源，被配置为在等离子体蚀刻装置内执行的蚀刻工艺的至少一部分期间将UV光输送到所述处理室。 提供了许多其他方面。

    PULSED DC PLASMA ETCHING PROCESS AND APPARATUS
    8.
    发明申请
    PULSED DC PLASMA ETCHING PROCESS AND APPARATUS 审中-公开
    脉冲直流等离子体蚀刻工艺和设备

    公开(公告)号：US20140273487A1

    公开(公告)日：2014-09-18

    申请号：US14200779

    申请日：2014-03-07

    Applicant: Applied Materials, Inc.

    Inventor： Subhash Deshmukh ,  He Ren ,  Jingjing Liu

    IPC: H01L21/3065 ,  H01L21/67

    CPC classification number: H01J37/32146 ,  H01J37/32091 ,  H01J37/32706 ,  H01J37/32715 ,  H01J37/32724 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/67069 ,  H01L21/68742 ,  H01L21/6875

    Abstract: In one aspect, a plasma etching apparatus is disclosed. The plasma etching apparatus includes a chamber body having a process chamber adapted to receive a substrate, an RF source coupled to an RF electrode, a pedestal located in the processing chamber and adapted to support a substrate, a plurality of conductive pins adapted to contact and support the substrate during processing, and a DC bias source electrically coupled to the plurality of conductive pins. Etching methods are provided, as are numerous other aspects.

    Abstract translation: 一方面，公开了一种等离子体蚀刻装置。 等离子体蚀刻装置包括具有适于接纳基板的处理室的室主体，耦合到RF电极的RF源，位于处理室中的基座，并适于支撑基板，多个导电引脚适于接触和 在处理期间支撑衬底，以及电耦合到多个导电引脚的DC偏压源。 提供了蚀刻方法，以及许多其它方面。

    RESIST HARDENING AND DEVELOPMENT PROCESSES FOR SEMICONDUCTOR DEVICE MANUFACTURING
    9.
    发明申请
    RESIST HARDENING AND DEVELOPMENT PROCESSES FOR SEMICONDUCTOR DEVICE MANUFACTURING 审中-公开
    用于半导体器件制造的耐腐蚀和开发工艺

    公开(公告)号：US20160329222A1

    公开(公告)日：2016-11-10

    申请号：US15216521

    申请日：2016-07-21

    Applicant: Applied Materials, Inc.

    Inventor： Peng Xie ,  Christopher Dennis Bencher ,  Huixiong Dai ,  Timothy Michaelson ,  Subhash Deshmukh

    IPC: H01L21/67 ,  H01L21/687 ,  C23C16/455

    CPC classification number: H01L21/67069 ,  C23C16/45544 ,  G03F7/36 ,  G03F7/405 ,  H01L21/67167 ,  H01L21/67201 ,  H01L21/68707

    Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.

    Abstract translation: 在一些实施例中，提供了在衬底上形成蚀刻掩模的方法，其包括（1）在衬底上形成抗蚀剂层; （2）将抗蚀剂层的一个或多个区域暴露于能量源，以便改变暴露区域的物理性质和化学性质中的至少一个; （3）对抗蚀剂层进行硬化处理以提高抗蚀剂层相对于抗蚀剂层的第二区域的第一区域的耐蚀刻性，硬化过程包括将抗蚀剂层暴露于原子层内的一个或多个反应性物质 沉积（ALD）室; 和（4）干蚀刻抗蚀剂层以除去一个或多个第二区域并在抗蚀剂层中形成图案。 提供其他实施例。

    RESIST HARDENING AND DEVELOPMENT PROCESSES FOR SEMICONDUCTOR DEVICE MANUFACTURING
    10.
    发明申请
    RESIST HARDENING AND DEVELOPMENT PROCESSES FOR SEMICONDUCTOR DEVICE MANUFACTURING 有权
    用于半导体器件制造的耐腐蚀和开发工艺

    公开(公告)号：US20140263172A1

    公开(公告)日：2014-09-18

    申请号：US14205324

    申请日：2014-03-11

    Applicant: Applied Materials, Inc.

    Inventor： Peng Xie ,  Christopher Dennis Bencher ,  Huixiong Dai ,  Timothy Michaelson ,  Subhash Deshmukh

    IPC: G03F7/36

    CPC classification number: H01L21/67069 ,  C23C16/45544 ,  G03F7/36 ,  G03F7/405 ,  H01L21/67167 ,  H01L21/67201 ,  H01L21/68707

    Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.

    Abstract translation: 在一些实施例中，提供了在衬底上形成蚀刻掩模的方法，其包括（1）在衬底上形成抗蚀剂层; （2）将抗蚀剂层的一个或多个区域暴露于能量源，以便改变暴露区域的物理性质和化学性质中的至少一个; （3）对抗蚀剂层进行硬化处理以提高抗蚀剂层相对于抗蚀剂层的第二区域的第一区域的耐蚀刻性，硬化过程包括将抗蚀剂层暴露于原子层内的一个或多个反应性物质 沉积（ALD）室; 和（4）干蚀刻抗蚀剂层以除去一个或多个第二区域并在抗蚀剂层中形成图案。 提供其他实施例。

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