公开(公告)号：US20210064377A1

公开(公告)日：2021-03-04

申请号：US16550612

申请日：2019-08-26

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA ,  Rakesh Shaji LAL ,  Michael FILIPPO ,  Glen Andrew HARRIS ,  Vasu KUDARAVALLI ,  Huzefa Moiz SANJELIWALA ,  Jason SETTER

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/34

Abstract: A data processing apparatus is provided that comprises fetch circuitry to fetch an instruction stream comprising a plurality of instructions, including a status updating instruction, from storage circuitry. Status storage circuitry stores a status value. Execution circuitry executes the instructions, wherein at least some of the instructions are executed in an order other than in the instruction stream. For the status updating instruction, the execution circuitry is adapted to update the status value based on execution of the status updating instruction. Flush circuitry flushes, when the status storage circuitry is updated, flushed instructions that appear after the status updating instruction in the instruction stream.

公开(公告)号：US20210026632A1

公开(公告)日：2021-01-28

申请号：US16521663

申请日：2019-07-25

Applicant: Arm Limited

Inventor： Miles Robert DOOLEY ,  Balaji VIJAYAN ,  Huzefa Moiz SANJELIWALA ,  . ABHISHEK RAJA ,  Sharmila SHRIDHAR

IPC: G06F9/30

Abstract: An apparatus is described, comprising load issuing circuitry configured to issue load operations to load data from memory, and memory ordering tracking storage circuitry configured to store memory ordering tracking information on issued load operations. The apparatus also includes control circuitry configured to access the memory ordering tracking storage circuitry to determine, using the memory ordering tracking information, whether at least one load operation has been issued in disagreement with a memory ordering requirement, and, if so, to determine whether to re-issue one or more issued load operations or to continue issuing load operations despite disagreement with the memory ordering requirement. Furthermore, the control circuitry is capable of merging the memory ordering tracking information for a plurality of issued load operations into a merged entry in the memory ordering tracking storage circuitry.

公开(公告)号：US20180253387A1

公开(公告)日：2018-09-06

申请号：US15446235

申请日：2017-03-01

Applicant: ARM Limited

Inventor： Huzefa Moiz SANJELIWALA ,  Klas Magnus BRUCE ,  Leigang KOU ,  Michael FILIPPO ,  Miles Robert DOOLEY ,  Matthew Andrew RAFACZ

IPC: G06F12/12 ,  G06F12/0897

CPC classification number: G06F12/0897 ,  G06F12/0862 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/60

Abstract: A data processing apparatus is provided that includes a plurality of storage elements. Receiving circuitry receives a plurality of incoming data beats from cache circuitry and stores the incoming data beats in the storage elements. At least one existing data beat in the storage elements is replaced by an equal number of the incoming data beats belonging to a different cache line of the cache circuitry. The existing data beats stored in said plurality of storage elements form an incomplete cache line.

公开(公告)号：US20210026627A1

公开(公告)日：2021-01-28

申请号：US16521748

申请日：2019-07-25

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA ,  Michael FILIPPO ,  Huzefa Moiz SANJELIWALA ,  Kelvin Domnic GOVEAS

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: Circuitry comprises an instruction decoder to decode a gather load instruction having a vector operand comprising a plurality of vector entries, in which each vector entry defines, at least in part, a respective address from which data is to be loaded; the instruction decoder being configured to generate a set of load operations relating to respective individual addresses in dependence upon the vector operand, each of the set of load operations having a respective identifier which is unique with respect to other load operations in the set, and control circuitry to maintain a data item for the gather load instruction, the data item including a count value representing a number of load operations in the set of load operations awaiting issue for execution; and execution circuitry to execute the set of load operations; the control circuitry being configured, in response to a detection from the count value of the data item associated with a given gather load instruction that the set of load operations generated for the given gather load instruction has reached a predetermined stage relative to execution of all of that set of load operations, to control handling of a consumer instruction, being an instruction which depends upon the completion of the given gather load instruction.

公开(公告)号：US20240126458A1

公开(公告)日：2024-04-18

申请号：US17966071

申请日：2022-10-14

Applicant: Arm Limited

Inventor： Stefano GHIGGINI ,  Natalya Bondarenko ,  Luca NASSI ,  Geoffray Matthieu LACOURBA ,  Huzefa Moiz SANJELIWALA ,  Miles Robert DOOLEY ,  . ABHISHEK RAJA

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673

Abstract: An apparatus is provided for controlling the operating mode of control circuitry, such that the control circuitry may change between two operating modes. In an allocation mode, data that is loaded in response to an instruction is allocated into storage circuitry from an intermediate buffer, and the data is read from the storage circuitry. In a non-allocation mode, the data is not allocated to the storage circuitry, and is read directly from intermediate buffer. The control of the operating mode may be performed by mode control circuitry, and the mode may be changed in dependence on the type of instruction that calls the data, and whether the data may be used again in the near future, or whether it is expected to be used only once.

公开(公告)号：US20180107604A1

公开(公告)日：2018-04-19

申请号：US15293467

申请日：2016-10-14

Applicant: ARM LIMITED

Inventor： Miles Robert DOOLEY ,  ABHISHEK RAJA ,  Barry Duane WILLIAMSON ,  Huzefa Moiz SANJELIWALA

IPC: G06F12/1009 ,  G06F12/0802

CPC classification number: G06F12/1009 ,  G06F12/0802 ,  G06F12/1027 ,  G06F2212/60 ,  G06F2212/651 ,  G06F2212/681 ,  G06F2212/682

Abstract: An apparatus and method are provided for maintaining address translation data within an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. The address translation cache is used to store address translation data of a plurality of different types representing address translation data specified at respective different levels of address translation within a multiple-level page table walk. The plurality of different types comprises a final level type of address translation data that identifies a full translation from the virtual address to the physical address, and at least one intermediate level type of address translation data that identifies a partial translation of the virtual address. The control circuitry is arranged, when performing the allocation process, to apply an allocation policy that permits each of the entries to be used for any of the different types of address translation data, and to store type identification data in association with each entry to enable the type of the address translation data stored therein to be determined. Such an approach enables very efficient usage of the address translation cache resources, for example by allowing the proportion of the entries used for full address translation data and the proportion of the entries used for partial address translation data to be dynamically adapted to changing workload conditions.

公开(公告)号：US20180095893A1

公开(公告)日：2018-04-05

申请号：US15281502

申请日：2016-09-30

Applicant: ARM LIMITED

Inventor： Miles Robert DOOLEY ,  Matthew Andrew RAFACZ ,  Huzefa Moiz SANJELIWALA ,  Michael FILIPPO

IPC: G06F12/1045 ,  G06F12/0862 ,  G06F12/0897

CPC classification number: G06F12/1045 ,  G06F9/30 ,  G06F9/3016 ,  G06F12/0862 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/50 ,  G06F2212/602

Abstract: A data processing apparatus is provided including queue circuitry to respond to control signals each associated with a memory access instruction, and to queue a plurality of requests for data, each associated with a reference to a storage location. Resolution circuitry acquires a request for data, and issues the request for data, the resolution circuitry having a resolution circuitry limit. When a current capacity of the resolution circuitry is below the resolution circuitry limit, the resolution circuitry acquires the request for data by receiving the request for data from the queue circuitry, stores the request for data in association with the storage location, issues the request for data, and causes a result of issuing the request for data to be provided to said storage location. When the current capacity of the resolution circuitry meets or exceeds the resolution circuitry limit, the resolution circuitry acquires the request for data by examining a next request for data in the queue circuitry and issues a further request for the data based on the request for data.