公开(公告)号：US20150031181A1

公开(公告)日：2015-01-29

申请号：US14195712

申请日：2014-03-03

Applicant: ADVANCED ION BEAM TECHNOLOGY, INC.

Inventor： Daniel TANG ,  Tzu-Shih YEN

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/165 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/31053 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Abstract translation: 形成具有在源极区和漏极区之间具有源极区，漏极区和沟道区的鳍的finFET。 翅片在半导体晶片上蚀刻。 形成具有与沟道区域直接接触的绝缘层和与绝缘层直接接触的导电栅极材料的栅极堆叠。 蚀刻源极和漏极区域，离开鳍片的沟道区域。 在与源极和漏极区相邻的沟道区的侧面上生长外延半导体，以形成源外延区和漏极外延区。 源极和漏极外延区域在生长外延半导体的同时原位掺杂。

公开(公告)号：US20140175568A1

公开(公告)日：2014-06-26

申请号：US14195605

申请日：2014-03-03

Applicant: ADVANCED ION BEAM TECHNOLOGY, INC.

Inventor： Daniel TANG ,  Tzu-Shih YEN

IPC: H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/31053 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Abstract translation: 形成具有在源极区和漏极区之间具有源极区，漏极区和沟道区的鳍的finFET。 翅片在半导体晶片上蚀刻。 形成具有与沟道区域直接接触的绝缘层和与绝缘层直接接触的导电栅极材料的栅极堆叠。 蚀刻源极和漏极区域，离开鳍片的沟道区域。 外延半导体在与源极和漏极区相邻的沟道区的侧面生长以形成源外延区和漏极外延区。 源极和漏极外延区域在生长外延半导体的同时原位掺杂。

公开(公告)号：US20160233047A1

公开(公告)日：2016-08-11

申请号：US15133619

申请日：2016-04-20

Applicant: Advanced Ion Beam Technology, Inc.

Inventor： Daniel TANG ,  Tienyu SHENG

IPC: H01J37/02 ,  H01J37/32 ,  H01L21/265

CPC classification number: H05H3/02 ,  H01J37/026 ,  H01J37/08 ,  H01J37/3171 ,  H01J37/3211 ,  H01J37/32357 ,  H01J37/32412 ,  H01J37/32422 ,  H01J37/3266 ,  H01J37/32688 ,  H01J2237/061 ,  H01J2237/083

Abstract: Systems and processes for plasma-based material modification of a work piece are provided. In an example process, a first plasma in a plasma source chamber is generated. A magnetic field is generated using a plurality of magnets. The magnetic field confines electrons of the first plasma having energy greater than 10 eV within the plasma source chamber. A second plasma is generated in a process chamber coupled to the plasma source chamber. An ion beam is generated in the process chamber by extracting ions from the first plasma through the plurality of magnets. The ion beam travels through the second plasma and is neutralized by the second plasma to generate a neutral beam. The work piece is positioned in the process chamber such that the neutral beam treats a surface of the work piece.

Abstract translation: 提供了工件等离子体材料改性的系统和工艺。 在示例性过程中，产生等离子体源室中的第一等离子体。 使用多个磁体产生磁场。 磁场限制等离子体源室内具有大于10eV的能量的第一等离子体的电子。 在耦合到等离子体源室的处理室中产生第二等离子体。 在处理室中通过从多个磁体中提取离子从第一等离子体中产生离子束。 离子束穿过第二等离子体并被第二等离子体中和以产生中性光束。 工件定位在处理室中，使得中性梁处理工件的表面。

公开(公告)号：US20140097487A1

公开(公告)日：2014-04-10

申请号：US13648127

申请日：2012-10-09

Applicant: ADVANCED ION BEAM TECHNOLOGY, INC.

Inventor： Tzu-Shih YEN ,  Daniel TANG ,  Tsungnan CHENG

IPC: H01L21/265 ,  H01L29/78

CPC classification number: H01L21/2236 ,  H01L29/66803 ,  H01L29/785

Abstract: In plasma doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. The substrate having the non-planar semiconductor body may be placed into a chamber. A plasma may be formed in the chamber and the plasma may contain dopant ions. A first bias voltage may be generated to implant dopant ions into a region of the non-planar semiconductor body. A second bias voltage may be generated to implant dopant ions into the same region. In one example, the first bias voltage and the second bias voltage may be different.

Abstract translation: 在等离子体掺杂非平面半导体器件中，获得其上形成有非平面半导体体的衬底。 具有非平面半导体本体的基板可以放置在室中。 等离子体可以在室中形成，等离子体可以含有掺杂离子。 可以产生第一偏置电压以将掺杂剂离子注入到非平面半导体本体的区域中。 可以产生第二偏置电压以将掺杂剂离子注入到相同的区域中。 在一个示例中，第一偏置电压和第二偏置电压可以不同。

公开(公告)号：US20160293734A1

公开(公告)日：2016-10-06

申请号：US14678874

申请日：2015-04-03

Applicant: Advanced Ion Beam Technology, Inc.

Inventor： Daniel TANG ,  Zhimin WAN ,  Ching-I LI ,  Ger-Pin LIN

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L29/10 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76237 ,  H01L29/1083

Abstract: In forming a punch-through stopper region in a fin field effect transistor (finFET) device, a substrate may be etched to form a pair of trenches that define a fin structure. A portion of a first dose of ions may be implanted into the substrate through a bottom wall of each trench to form a pair of first dopant regions that at least partially extend under a channel region of the fin structure. The substrate at the bottom wall of each trench may be etched to increase a depth of each trench. Etching the substrate at the bottom wall of each trench may remove a portion of each first dopant region under each trench. A remaining portion of the pair of first dopant regions under the fin structure may at least partially define the punch-through stopper region of the finFET device.

Abstract translation: 在鳍状场效应晶体管（finFET）器件中形成穿通停止区域时，可蚀刻衬底以形成限定翅片结构的一对沟槽。 第一剂量的离子的一部分可以通过每个沟槽的底壁注入到衬底中，以形成至少部分地延伸在翅片结构的沟道区域下面的一对第一掺杂区域。 可以蚀刻每个沟槽的底壁处的衬底以增加每个沟槽的深度。 在每个沟槽的底壁处蚀刻衬底可以去除每个沟槽下的每个第一掺杂剂区域的一部分。 翅片结构下面的一对第一掺杂剂区域的剩余部分可以至少部分地限定finFET器件的穿通阻挡区域。