公开(公告)号：US20240329720A1

公开(公告)日：2024-10-03

申请号：US18128744

申请日：2023-03-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gia Tung Phan ,  Ashish Jain ,  Anthony Asaro ,  Dennis Kin-Wah Au

IPC: G06F1/3234 ,  G09G5/00

CPC classification number: G06F1/3265 ,  G09G5/001 ,  G09G5/363 ,  G09G2300/0842 ,  G09G2330/021 ,  G09G2360/123 ,  G09G2360/18

Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated memories that use separate power domains. Data of a given type is stored in an interleaved manner among the multiple memories. When control circuitry detects an idle state, commands are sent to the multiple memories specifying storing data of the given type in a contiguous manner in the memories connected to multiple functional blocks. Subsequently, the control circuitry transitions all but one of the memories to the sleep state. The memories rotate amongst themselves with a single memory being in the active state and servicing requests based on which data of the given type is targeted by the requests.

公开(公告)号：US20240211023A1

公开(公告)日：2024-06-27

申请号：US18146811

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gia Tung Phan ,  Ashish Jain ,  Shang Yang

IPC: G06F1/3296 ,  G06F12/0875 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F1/3296 ,  G06F12/0875 ,  G06T1/20 ,  G06T1/60 ,  G06F2212/45

Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among at least two of the multiple functional blocks. In one implementation, a prior static allocation determines that only a subset of the functional blocks store the data of the given type. In another implementation, each of the functional blocks stores the data of the given type, and when an idle state has occurred, data of the given type is moved between the multiple functional blocks until one or more functional blocks no longer store data of the given type. When a transition to the idle state has occurred, the functional blocks that do not store the data of the given type are transitioned to a sleep state.

公开(公告)号：US11899520B2

公开(公告)日：2024-02-13

申请号：US17730041

申请日：2022-04-26

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Benjamin Tsien ,  Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Shang Yang

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3234 ,  G06F12/0891

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F12/0891 ,  G06F2212/1021 ,  G06F2212/1028

Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.

公开(公告)号：US20240004725A1

公开(公告)日：2024-01-04

申请号：US17854650

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Shang Yang ,  Arash Moghimi

IPC: G06F9/50

CPC classification number: G06F9/5094 ,  G06F9/505 ,  G06F9/5038

Abstract: Systems, apparatuses, and methods for managing power allocation in a computing system. A system management unit detects a condition indicating a change in power is indicated. Such a change may be detecting an indication that a power change is either required, possible, or requested. In response to detecting a reduction in power is indicated, the system management unit identifies currently executing tasks of the computing system and accesses sensitivity data to determine which of a number of computing units (or power domains) to select for power reduction. Based at least in part on the data, a unit is identified that is determined to have a relatively low sensitivity to power state changes under the current operating conditions. A relatively low sensitivity indicates that a change in power to the corresponding unit will not have as significant an impact on overall performance of the computing system than if another unit was selected. Power allocated for the selected unit is then decreased.

公开(公告)号：US20220414222A1

公开(公告)日：2022-12-29

申请号：US17356776

申请日：2021-06-24

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Gia Phan ,  Ashish Jain ,  Randall Brown

IPC: G06F21/57 ,  G06F21/60 ,  G06F9/46 ,  G06F9/50 ,  G06T1/20

Abstract: A trusted processor saves and restores context and data stored at a frame buffer of a GPU concurrent with initialization of a CPU of the processing system. In response to detecting that the GPU is powering down, the trusted processor accesses the context of the GPU and data stored at a frame buffer of the GPU via a high-speed bus. The trusted processor stores the context and data at a system memory, which maintains the context and data while the GPU is powered down. In response to detecting that the GPU is powering up again, the trusted processor restores the context and data to the GPU, which can be performed concurrently with initialization of the CPU.

公开(公告)号：US20240419481A1

公开(公告)日：2024-12-19

申请号：US18334363

申请日：2023-06-13

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Ashkan Hosseinzadeh Namin

IPC: G06F9/46

Abstract: An apparatus and method for efficiently performance among replicated functional blocks of an integrated circuit despite different circuit behavior amongst the functional blocks due to manufacturing variations. An integrated circuit includes multiple replicated functional blocks, each being a semiconductor die with an instantiated copy of particular integrated circuitry for processing a work block. One or more of the functional blocks of the integrated circuit belong in a different performance category or bin than other functional blocks due to manufacturing variations across semiconductor dies. A scheduler assigns work blocks to the functional blocks based on whether a functional block is from a high-performance bin and whether a workload of a work block is a computation intensive workload. The scheduler assigns work blocks work blocks marked as having a memory access intensive workload to functional blocks from a lower performance bin.

公开(公告)号：US20240106438A1

公开(公告)日：2024-03-28

申请号：US18525071

申请日：2023-11-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Kaushik Mazumdar ,  Ashish Jain ,  Joyce Cheuk Wai Wong ,  Mikhail Rodionov

IPC: H03L7/08 ,  G01R19/165

CPC classification number: H03L7/08 ,  G01R19/16552

Abstract: An integrated circuit includes a power supply monitor, a clock generator, and a divider. The power supply monitor is operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage. The clock generator is operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency control word. The divider is responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.

公开(公告)号：US20230341922A1

公开(公告)日：2023-10-26

申请号：US17730041

申请日：2022-04-26

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Benjamin Tsien ,  Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Shang Yang

IPC: G06F1/3287 ,  G06F1/3234 ,  G06F12/0891

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F12/0891 ,  G06F2212/1021 ,  G06F2212/1028

Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.

公开(公告)号：US12164365B2

公开(公告)日：2024-12-10

申请号：US18146811

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gia Tung Phan ,  Ashish Jain ,  Shang Yang

IPC: G06F1/3296 ,  G06F12/0875 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among at least two of the multiple functional blocks. In one implementation, a prior static allocation determines that only a subset of the functional blocks store the data of the given type. In another implementation, each of the functional blocks stores the data of the given type, and when an idle state has occurred, data of the given type is moved between the multiple functional blocks until one or more functional blocks no longer store data of the given type. When a transition to the idle state has occurred, the functional blocks that do not store the data of the given type are transitioned to a sleep state.

公开(公告)号：US20240331659A1

公开(公告)日：2024-10-03

申请号：US18128797

申请日：2023-03-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gia Tung Phan ,  Dennis Kin-Wah Au ,  Oswin Hall ,  Ashish Jain

IPC: G09G5/36

CPC classification number: G09G5/363 ,  G09G2330/021 ,  G09G2360/123

Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among the multiple functional blocks. When control circuitry detects a low-performance mode, commands are sent to the multiple functional blocks specifying storing data of the given type in a contiguous manner in one or more of the caches of the multiple functional blocks and the memories connected to the multiple functional blocks. Following, the control circuitry transitions the memories to a sleep state and transitions all but one of the functional blocks to the sleep state. The functional blocks rotate amongst themselves with a single functional block being in the active state and servicing requests based on which data of the given type is targeted by the requests.