公开(公告)号：US20160233169A1

公开(公告)日：2016-08-11

申请号：US15133994

申请日：2016-04-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard Hunt

IPC: H01L23/538 ,  H01L25/00 ,  H01L25/11 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.

公开(公告)号：US10276382B2

公开(公告)日：2019-04-30

申请号：US15615665

申请日：2017-06-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard Hunt ,  William T. Chen ,  Chih-Pin Hung ,  Chen-Chao Wang

IPC: H01L21/00 ,  H01L21/108 ,  H01L21/768 ,  H01L23/04 ,  H01L23/48 ,  H01L23/485 ,  H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L27/108 ,  H01L23/16 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538 ,  H01L23/31

Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.

公开(公告)号：US09343333B2

公开(公告)日：2016-05-17

申请号：US14577942

申请日：2014-12-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard Hunt

IPC: H01L21/311 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.

公开(公告)号：US20150140737A1

公开(公告)日：2015-05-21

申请号：US14577942

申请日：2014-12-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard Hunt

IPC: H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.

Abstract translation: 半导体封装包括具有活性表面的至少一个半导体管芯，具有上表面和下表面的插入元件，封装主体和下再分布层。 插入器元件具有在上表面和下表面之间延伸的至少一个导电通孔。 封装体封装半导体管芯的部分和内插器元件的部分。 下再分布层将插入元件电连接到半导体管芯的有源表面。

公开(公告)号：US10886263B2

公开(公告)日：2021-01-05

申请号：US15721257

申请日：2017-09-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： William T. Chen ,  John Richard Hunt ,  Chih-Pin Hung ,  Chen-Chao Wang ,  Chih-Yi Huang

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H01L23/13 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H01L25/04 ,  H01L25/065

Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.

公开(公告)号：US10515806B2

公开(公告)日：2019-12-24

申请号：US16297477

申请日：2019-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard Hunt ,  William T. Chen ,  Chih-Pin Hung ,  Chen-Chao Wang

IPC: H01L23/48 ,  H01L21/108 ,  H01L23/00 ,  H01L23/04 ,  H01L21/768 ,  H01L23/485 ,  H01L25/065 ,  H01L21/683 ,  H01L23/538 ,  H01L23/16 ,  H01L21/56 ,  H01L27/108 ,  H01L23/528 ,  H01L23/31

Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the second portion of the first trace is disposed between and spaced from opposing sidewalls of the dielectric layer defining the first opening.

公开(公告)号：US10916429B2

公开(公告)日：2021-02-09

申请号：US16705018

申请日：2019-12-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard Hunt ,  William T. Chen ,  Chih-Pin Hung ,  Chen-Chao Wang

IPC: H01L21/00 ,  H01L21/108 ,  H01L23/16 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/768 ,  H01L23/04 ,  H01L23/48 ,  H01L23/485 ,  H01L23/528 ,  H01L25/065 ,  H01L27/108 ,  H01L23/31

Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.

公开(公告)号：US10535521B2

公开(公告)日：2020-01-14

申请号：US16297480

申请日：2019-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard Hunt ,  William T. Chen ,  Chih-Pin Hung ,  Chen-Chao Wang

IPC: H01L21/00 ,  H01L21/108 ,  H01L23/16 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/768 ,  H01L23/04 ,  H01L23/48 ,  H01L23/485 ,  H01L23/528 ,  H01L25/065 ,  H01L27/108 ,  H01L23/31

Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the second portion of the first trace is disposed between and spaced from opposing sidewalls of the dielectric layer defining the first opening.