公开(公告)号：US20210305406A1

公开(公告)日：2021-09-30

申请号：US17346271

申请日：2021-06-13

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/808 ,  H01L29/06 ,  H01L27/07

摘要： A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

公开(公告)号：US10998264B2

公开(公告)日：2021-05-04

申请号：US17060083

申请日：2020-10-01

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Jun Hu ,  Madhur Bobde ,  Hamza Yilmaz

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/739 ,  H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56 ,  H01L23/31

摘要： A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

公开(公告)号：US20190157384A1

公开(公告)日：2019-05-23

申请号：US16258662

申请日：2019-01-27

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Jun Hu ,  Madhur Bobde ,  Hamza Yilmaz

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/739 ,  H01L29/66 ,  H01L21/265 ,  H01L29/40

CPC分类号： H01L29/0623 ,  H01L21/265 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397

摘要： A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

公开(公告)号：US10243072B2

公开(公告)日：2019-03-26

申请号：US15971624

申请日：2018-05-04

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Madhur Bobde ,  Lingpeng Guan ,  Karthik Padmanabhan ,  Hamza Yilmaz

IPC分类号： H01L21/84 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417

摘要： A method for forming a lateral superjunction MOSFET device includes forming a semiconductor body including a lateral superjunction structure and a first column connected to the lateral superjunction structure. The MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second column disposed in close proximity to the first column. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.

公开(公告)号：US10192982B2

公开(公告)日：2019-01-29

申请号：US15680712

申请日：2017-08-18

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L27/088 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06

摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device includes a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each trench has a first dimension (depth), a a second dimension (width) and a third dimension (length). The body region is of opposite conductivity type to the lightly and heavily doped layers. An opening is formed between first and second trenches through an upper portion of the source region and a body contact region to the body region. A deep implant region of the second conductivity type is formed in the lightly doped layer below the body region. The deep implant region is vertically aligned to the opening and spaced away from a bottom of the opening.

公开(公告)号：US20180254342A1

公开(公告)日：2018-09-06

申请号：US15971624

申请日：2018-05-04

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Madhur Bobde ,  Lingpeng Guan ,  Karthik Padmanabhan ,  Hamza Yilmaz

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/40 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7816

摘要： A method for forming a lateral superjunction MOSFET device includes forming a semiconductor body including a lateral superjunction structure and a first column connected to the lateral superjunction structure. The MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second column disposed in close proximity to the first column. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.

公开(公告)号：US10069005B2

公开(公告)日：2018-09-04

申请号：US15425235

申请日：2017-02-06

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

摘要： The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US10032861B2

公开(公告)日：2018-07-24

申请号：US15721892

申请日：2017-09-30

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  Madhur Bobde

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L27/082 ,  H01L27/088 ,  H01L29/78 ,  H01L29/40 ,  H01L29/739

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.

公开(公告)号：US09960237B2

公开(公告)日：2018-05-01

申请号：US14684570

申请日：2015-04-13

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/04

CPC分类号： H01L29/407 ,  H01L21/76205 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

公开(公告)号：US09876096B2

公开(公告)日：2018-01-23

申请号：US15336636

申请日：2016-10-27

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Madhur Bobde ,  Sik Lui ,  Hamza Yilmaz ,  Jongoh Kim ,  Daniel Ng

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/40 ,  H01L29/36 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/872

CPC分类号： H01L29/66734 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66492 ,  H01L29/66666 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L29/8725

摘要： A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches. One or more source regions of the first conductivity type are formed in a top portion of the epitaxial region between a contact trench and a gate trench. A barrier metal is formed inside each contact trench.Each gate trench is substantially filled with a conductive material separated from trench walls by a layer of dielectric material to form a gate . A heavily doped well region of a conductivity opposite the first type is provided in the epitaxial region proximate a bottom portion of each of the contact trenches. A horizontal width of a gap between the well region and the gate trench is about 0.05 μm to 0.2 μm.