公开(公告)号：US12056067B1

公开(公告)日：2024-08-06

申请号：US17039125

申请日：2020-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Jonathan Cohen ,  Said Bshara ,  Leah Shalev ,  Erez Izenberg ,  Rotem Shaanan

IPC: G06F13/16 ,  G06F9/30 ,  G06F13/28 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F13/1673 ,  G06F9/30101 ,  G06F13/161 ,  G06F13/1642 ,  G06F13/28 ,  G06F15/17375 ,  G06F15/7807

Abstract: Systems and methods are provided to reduce the latency in accessing an input/output (I/O) hardware register by software executing on a central processing unit (CPU). The hardware register is located in a controller coupled to the CPU via an I/O bus. The CPU software can send a command to the controller for execution. The controller can execute the command and update the hardware register to indicate that the command has been executed. The controller can write contents of the hardware register to a specified address in a CPU memory that is assigned by the CPU software. The CPU software can read the specified address to determine that the command has been executed instead of reading the hardware register on the I/O bus.

公开(公告)号：US10708246B1

公开(公告)日：2020-07-07

申请号：US15836292

申请日：2017-12-08

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Noa Yehezkel ,  Ahmad Erew ,  Jonathan Cohen ,  Michael Baranchik

IPC: H04L29/06 ,  G06F9/455 ,  H04L12/801 ,  H04L12/861

Abstract: An apparatus and a corresponding method. The apparatus includes an injection module operable to maintain packet sequence numbers for a group of network devices, receive a first packet and a second packet that is sent from the apparatus after the first packet and destined for a different device in the group than the first packet, and update the packets with different packet sequence numbers. The packet sequence number for the second packet is generated using the packet sequence number for the first packet. The apparatus further includes an encryption module operable to determine an initialization vector for each packet sequence number and apply an encryption algorithm to each packet. Each packet is encrypted using a corresponding initialization vector and an encryption key as inputs to the encryption algorithm.

公开(公告)号：US10559345B1

公开(公告)日：2020-02-11

申请号：US16191356

申请日：2018-11-14

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Jonathan Cohen ,  Elad Valfer

IPC: G11C8/00 ,  G11C11/408 ,  G06F12/06 ,  G11C13/00 ,  G11C8/12 ,  G11C7/10 ,  G11C8/10

Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.

公开(公告)号：US12175285B1

公开(公告)日：2024-12-24

申请号：US17305151

申请日：2021-06-30

Applicant: Amazon Technologies, Inc.

Inventor： Nitzan Zisman ,  Said Bshara ,  Erez Izenberg ,  Avigdor Segal ,  Jonathan Cohen ,  Anna Rom-Saksonov ,  Leah Shalev ,  Shadi Ammouri

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/355 ,  G06F9/50 ,  G06F13/28

Abstract: An integrated circuit for distributing processing tasks includes a pre-selector circuit and a scheduler circuit. The pre-selector circuit is configured to receive a processing task, determine a category of the processing task, and select, from a set of task distribution techniques and based at least in part on the category of the processing task, a task distribution technique for distributing the processing task to a group of processing units. The scheduler circuit is configured to implement the selected task distribution technique to select, from the group of processing units, a target processing unit for performing the processing task.

公开(公告)号：US11386008B1

公开(公告)日：2022-07-12

申请号：US17018105

申请日：2020-09-11

Applicant: Amazon Technologies, inc.

Inventor： Anna Rom-Saksonov ,  Erez Izenberg ,  Avigdor Segal ,  Jonathan Cohen ,  Nitzan Zisman ,  Noam Attias

IPC: G06F12/0846 ,  G06F12/02 ,  G06F11/10 ,  G06F11/07 ,  G11C15/00 ,  G11C15/04

Abstract: A memory apparatus for detecting false hits in a content-addressable memory (CAM) is disclosed. The memory apparatus includes a controller coupled to the CAM and a memory. The controller receives a search result including an address from the CAM, the address corresponding to a matching entry from a first set of data entries that matches a search tag. The controller provides a read address based on the address to the memory, which returns a second data entry from a second set of data entries corresponding to the read address. The controller receives the read data and generates an error detection result based on a comparison between the second data entry and the search tag.

公开(公告)号：US11954495B1

公开(公告)日：2024-04-09

申请号：US17643777

申请日：2021-12-10

Applicant: Amazon Technologies, Inc.

Inventor： Michael Shteinbok ,  Yaniv Halmut ,  Jonathan Cohen ,  Nofar Mann ,  Tamir Malka ,  Amit Abecasis ,  Assaf Fainer

IPC: G06F9/38 ,  G06F16/245 ,  G06F16/2455

CPC classification number: G06F9/3877 ,  G06F16/245 ,  G06F16/2455 ,  G06F16/24569

Abstract: To accelerate the data processing of a processor, a coprocessor subsystem can be used to offload data processing operations from the processor. The coprocessor subsystem can include a coprocessor and an accelerator. The accelerator can offload operations such as data formatting operations from the coprocessor to improve the performance of the coprocessor. The coprocessor subsystem can be used to accelerate database operations.

公开(公告)号：US11899969B1

公开(公告)日：2024-02-13

申请号：US17805633

申请日：2022-06-06

Applicant: Amazon Technologies, Inc.

Inventor： Barak Singer ,  Guy Nakibly ,  Jonathan Cohen ,  Simaan Bahouth

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: Techniques are described for maintaining in-order execution when a dependency exists between write transactions. In some embodiments, a write re-order buffer (WROB) is configured to assign the same group ID to an incoming write transaction upon determining that the incoming write transaction is dependent on a pending write transaction. The WROB forwards the incoming write transaction to an interconnect fabric for routing to a completer device. The interconnect fabric enforces in-order execution when write transactions share the same group ID. The WROB can maintain a transaction log of pending write transactions and also track the statuses of responses for such transactions. Transaction responses can include responses sent from a completer to confirm that a transaction has actually been completed. Additionally, the WROB can send a response indicating completion back to the requester of the transaction. In some embodiments, the WROB is configured to send an early response to the requester.

公开(公告)号：US11467998B1

公开(公告)日：2022-10-11

申请号：US17203231

申请日：2021-03-16

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Said Bshara ,  Jonathan Cohen ,  Avigdor Segal

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/28 ,  G06F15/173 ,  G06F15/78 ,  G06F9/46

Abstract: Techniques for low-latency packet processing are disclosed. A network device receives a first set of write transactions including a first set of data segments corresponding to a first DMA descriptor from a host. The network device receives a second set of write transactions including a second set of data segments corresponding to a second DMA descriptor from the host. The network device detects that the first set of data segments have been written. In response to detecting that the first set of data segments have been written, and prior to completely writing the second set of data segments and to receiving a packet notifier from the host, the network device processes the first DMA descriptor.

公开(公告)号：US10134464B1

公开(公告)日：2018-11-20

申请号：US15468704

申请日：2017-03-24

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Jonathan Cohen ,  Elad Valfer

IPC: G11C8/00 ,  G11C11/408 ,  G11C13/00

Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.

公开(公告)号：US09607682B1

公开(公告)日：2017-03-28

申请号：US15083077

申请日：2016-03-28

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Jonathan Cohen ,  Elad Valfer

IPC: G11C8/00 ,  G11C11/408 ,  G11C7/10 ,  G11C8/12 ,  G11C8/10

CPC classification number: G11C11/4087 ,  G06F12/06 ,  G06F2212/1041 ,  G11C7/1006 ,  G11C8/10 ,  G11C8/12

Abstract: A decoder is disclosed that is used to select an area of address space in an Integrated Circuit. The decoder uses a hardware shifting module that performs shift operations on constants. Such a structure reduces an overall area consumption of the shifting module. Additionally, the decoder can perform a multi-bit shift operation in a single clock cycle.