公开(公告)号：US5630153A

公开(公告)日：1997-05-13

申请号：US317783

申请日：1994-10-04

申请人： Amos Intrater ,  Moshe Doron ,  Gideon Intrater ,  Lev Epstein ,  Maurice Valentaten ,  Israel Greiss

发明人： Amos Intrater ,  Moshe Doron ,  Gideon Intrater ,  Lev Epstein ,  Maurice Valentaten ,  Israel Greiss

IPC分类号： G06J3/00 ,  G06F9/38 ,  G06F15/78 ,  H04L27/00 ,  H04M11/00 ,  H04N1/40 ,  G06F9/26 ,  G06F9/40 ,  G06F9/44 ,  G06F13/36

CPC分类号： H04L27/00 ,  G06F15/7842 ,  G06F9/3885

摘要： An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks. While in many applications the data processing system will include an analog front end that converts a modulated input signal received on an analog transmission channel to a corresponding digital signal for processing by the data processing system, the data processing system may also receive the digital signal directly from a digital source.

摘要翻译： 一种用于处理包括通用处理器和数字信号处理器（DSP）模块的数字信号的集成数据处理平台。 DSP模块利用通用处理器选择的一系列DSP操作，从数字信号中恢复数字数据。 通用处理器处理由DSP模块恢复的数字数据，但也可用于执行通用任务。 共享内部存储器阵列选择性地向DSP模块和通用处理器提供信息。 存储在内部存储器阵列中的信息包括在DSP算法的执行中使用的操作数和通用CPU所使用的选择的指令和数据，用于控制DSP算法的执行或用于执行其自己的通用任务。 在许多应用中，数据处理系统将包括模拟前端，将模拟传输通道上接收的调制输入信号转换为相应的数字信号，以供数据处理系统处理，数据处理系统也可以直接接收数字信号 从数字来源。

公开(公告)号：USRE40942E1

公开(公告)日：2009-10-20

申请号：US09234427

申请日：1999-01-20

申请人： Amos Intrater ,  Gideon Intrater ,  Moshe Doron ,  Lev Epstein ,  Maurice Valentaten ,  Israel Greiss

发明人： Amos Intrater ,  Gideon Intrater ,  Moshe Doron ,  Lev Epstein ,  Maurice Valentaten ,  Israel Greiss

IPC分类号： G06F9/26 ,  G06F9/40 ,  G06F13/36

CPC分类号： H04L27/00 ,  G06F9/3885 ,  G06F15/7842

摘要： An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks. While in many applications the data processing system will include an analog front end that converts a modulated input signal received on an analog transmission channel to a corresponding digital signal for processing by the data processing system, the data processing system may also receive the digital signal directly from a digital source.

摘要翻译： 一种用于处理包括通用处理器和数字信号处理器（DSP）模块的数字信号的集成数据处理平台。 DSP模块利用通用处理器选择的一系列DSP操作，从数字信号中恢复数字数据。 通用处理器处理由DSP模块恢复的数字数据，但也可用于执行通用任务。 共享内部存储器阵列选择性地向DSP模块和通用处理器提供信息。 存储在内部存储器阵列中的信息包括在DSP算法的执行中使用的操作数和由通用CPU使用的选择的指令和数据，用于控制DSP算法的执行或用于执行其自己的通用任务。 在许多应用中，数据处理系统将包括模拟前端，将模拟传输通道上接收的调制输入信号转换为相应的数字信号，以便由数据处理系统进行处理，数据处理系统也可以直接接收数字信号 从数字来源。

公开(公告)号：US5592677A

公开(公告)日：1997-01-07

申请号：US246554

申请日：1994-05-19

申请人： Amos Intrater ,  Andy Birenbaum ,  Gideon Intrater ,  Iddo Carmon ,  Ilan Shimony ,  Itael Fraenkel ,  Lev Epstein ,  Lior Katzri ,  Omri Viner ,  Raya Levitan ,  Ronny Cohen ,  Sidi Yomtov ,  Yehezkel Tzadik ,  Zvi Greenfeld ,  Israel Greiss ,  Oved Oz ,  Yachin Afek ,  Meir Tsadik ,  Moshe Doron ,  Alberto Sandbank

发明人： Amos Intrater ,  Andy Birenbaum ,  Gideon Intrater ,  Iddo Carmon ,  Ilan Shimony ,  Itael Fraenkel ,  Lev Epstein ,  Lior Katzri ,  Omri Viner ,  Raya Levitan ,  Ronny Cohen ,  Sidi Yomtov ,  Yehezkel Tzadik ,  Zvi Greenfeld ,  Israel Greiss ,  Oved Oz ,  Yachin Afek ,  Meir Tsadik ,  Moshe Doron ,  Alberto Sandbank

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F13/00

CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

摘要翻译： 集成的数据处理系统包括用于传送指令和数据的共享内部总线。 共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线 。 通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。 连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。 共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

公开(公告)号：US5590357A

公开(公告)日：1996-12-31

申请号：US301739

申请日：1994-09-06

申请人： Amos Intrater ,  Andy Birenbaum ,  Gideon Intrater ,  Iddo Carmon ,  Ilan Shimony ,  Itael Fraenkel ,  Lev Epstein ,  Lior Katzri ,  Omri Viner ,  Raya Levitan ,  Ronny Cohen ,  Sidi Yomtov ,  Yehezkel Tzadik ,  Zvi Greenfeld ,  Israel Greiss ,  Oved Oz ,  Yachin Afek ,  Meir Tsadik ,  Moshe Doron ,  Alberto Sandbank

发明人： Amos Intrater ,  Andy Birenbaum ,  Gideon Intrater ,  Iddo Carmon ,  Ilan Shimony ,  Itael Fraenkel ,  Lev Epstein ,  Lior Katzri ,  Omri Viner ,  Raya Levitan ,  Ronny Cohen ,  Sidi Yomtov ,  Yehezkel Tzadik ,  Zvi Greenfeld ,  Israel Greiss ,  Oved Oz ,  Yachin Afek ,  Meir Tsadik ,  Moshe Doron ,  Alberto Sandbank

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F13/12

CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

摘要翻译： 集成数据处理系统包括用于传送指令和数据的共享内部总线。 共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线 。 通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 OP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。 连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。 共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

公开(公告)号：US5818251A

公开(公告)日：1998-10-06

申请号：US661455

申请日：1996-06-11

申请人： Amos Intrater

发明人： Amos Intrater

IPC分类号： G01R31/28 ,  G01R31/26

CPC分类号： G01R31/2812 ,  G01R31/048 ,  G01R31/2853

摘要： Apparatus and method for testing the connection (i.e. solder joint) between an input/output (I/O) pin of an integrated circuit and a conductive trace of a printed circuit board (PCB). The internal circuitry of the integrated circuit is isolated from each I/O pin, and a first voltage source is coupled to each I/O pin via a respective pull-up load resistor. A tester circuit is coupled to each conductive trace of the PCB and compares the voltage V.sub.T thereon with a high threshold level (HTVL) and a low threshold level (LTVL) to test for a proper connection. Voltage V.sub.T is derived for an I/O pin under test when a resistive element, which is part of the tester circuit, is operatively coupled between the corresponding conductive trace and a second voltage source. If V.sub.T is below the LTVL or above the HTVL, the I/O pin is improperly coupled to the conductive trace. If V.sub.T is between the LTVL and HTVL, then the voltage on each of the other traces is compared to the HTVL. If the voltage level of one of the other traces not under test is below the HTVL, then the other I/O pin is electrically shorted to the I/O pin under test.

摘要翻译： 用于测试集成电路的输入/输出（I / O）引脚与印刷电路板（PCB）的导电迹线之间的连接（即焊点）的装置和方法。 集成电路的内部电路与每个I / O引脚隔离，第一个电压源通过相应的上拉负载电阻耦合到每个I / O引脚。 测试器电路耦合到PCB的每个导电迹线，并将其上的电压VT与高阈值电平（HTVL）和低阈值电平（LTVL）进行比较，以测试正确的连接。 当作为测试器电路的一部分的电阻元件可操作地耦合在对应的导电迹线和第二电压源之间时，为测试的I / O引脚导出电压VT。 如果VT低于LTVL或高于HTVL，则I / O引脚不正确地耦合到导电迹线。 如果VT位于LTVL和HTVL之间，则将其他每条迹线上的电压与HTVL进行比较。 如果未测试的其他轨迹之一的电压电平低于HTVL，则另一个I / O引脚与被测I / O引脚电短路。

公开(公告)号：US5867718A

公开(公告)日：1999-02-02

申请号：US564952

申请日：1995-11-29

申请人： Amos Intrater ,  Erez Bar-Niv

发明人： Amos Intrater ,  Erez Bar-Niv

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3215 ,  G06F1/26

摘要： A method and apparatus for waking up a computer system using a peripheral device connected to a standard parallel port of the computer system. Functionality is added to the parallel port Select line normally used to indicate that the peripheral device connected to the parallel port is on line when the select signal is high. A signal transition on the Select line from low to high is detected and used to wake up the computer system. This toggling of the Selected line is detected and used to activate the computer system power supply into a normal operating state from a power save state.

摘要翻译： 一种使用连接到计算机系统的标准并行端口的外围设备来唤醒计算机系统的方法和装置。 功能被添加到并行端口选择线，通常用于指示连接到并行端口的外围设备在选择信号为高电平时为在线。 检测到Select Line从低电平到高电平的信号转换，并用于唤醒计算机系统。 检测到该选择行的切换，并用于从计算机状态激活计算机系统电源进入正常工作状态。

公开(公告)号：US5263153A

公开(公告)日：1993-11-16

申请号：US573287

申请日：1990-08-24

申请人： Amos Intrater ,  Donald B. Alpert

发明人： Amos Intrater ,  Donald B. Alpert

IPC分类号： G06F11/36 ,  G06F11/30

CPC分类号： G06F11/3636

摘要： A method for monitoring the sequence of instructions executed by a central processing unit. When a branch instruction is executed, the central processing unit generates a representative interface signal. When a jump instruction is executed or an exception occurs, the central processing unit displays representative information on the external memory interface.

摘要翻译： 一种用于监视由中央处理单元执行的指令序列的方法。 当执行分支指令时，中央处理单元生成代表性的接口信号。 当执行跳转指令或发生异常时，中央处理单元在外部存储器接口上显示代表性信息。

公开(公告)号：US5218314A

公开(公告)日：1993-06-08

申请号：US890691

申请日：1992-05-29

申请人： Avner Efendovich ,  Afek Yachin ,  Amos Intrater ,  Zohar Peleg ,  Coby Sella ,  Zeev Bikowsky

发明人： Avner Efendovich ,  Afek Yachin ,  Amos Intrater ,  Zohar Peleg ,  Coby Sella ,  Zeev Bikowsky

IPC分类号： H03L7/00

CPC分类号： H03L7/00

摘要： The present invention provides a phase-locked loop in which an internal oscillator is fed into a high resolution tapped delay line. One output of the tapped delay line is selected by selection logic to generate the output clock. The output clock is phase compared with the input signal, which is either a clock signal or a NRZ data signal, and in any case, is a signal with frequency that is a division by two of the frequency of the internal oscillator and the source of which is also the internal oscillator. Then a decision is made, according to the phase detection, whether to select the next output of the delay line, the previous one, or remain with the current one. Therefore, if a change in the frequency is needed, then if an integer multiple or division of the original frequency is selected for the internal oscillator, synchronization will be unchanged, and furthermore, both the output clock and the input signal will simultaneously switch to the new frequency. All this is done by additional logic that enables actual switching to the new frequency only after an entire cycle of the low frequency has ended.

摘要翻译： 本发明提供一种锁相环，其中将内部振荡器馈入高分辨率抽头延迟线。 抽头延迟线的一个输出由选择逻辑选择以产生输出时钟。 输出时钟与输入信号进行相位比较，输入信号是时钟信号或NRZ数据信号，在任何情况下都是频率为内部振荡器的频率除以2的信号， 这也是内部振荡器。 然后，根据相位检测，决定是选择延迟线的下一个输出，前一个还是与当前延迟线保持一致。 因此，如果需要频率变化，则如果为内部振荡器选择原始频率的整数倍或除法，同步将不变，此外，输出时钟和输入信号都将同时切换到 新频率 所有这些都是通过额外的逻辑完成的，只有在低频的整个周期结束后才能实际切换到新频率。