公开(公告)号：US20250087573A1

公开(公告)日：2025-03-13

申请号：US18464926

申请日：2023-09-11

Applicant: Applied Materials, Inc.

Inventor： Tyler Sherwood ,  Raghav Sreenivasan ,  Michael Chudzik ,  Maria Gorchichko

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/64

Abstract: The interconnect resistances in a hybrid bonded structure can be controlled and designed. The resistance of each interconnect can be controlled by the width of the vias, the number of vias, and the thickness of liners within the vias. A first interconnect and a second interconnect of a hybrid bonded structure can have different interconnect resistances despite being on the same wafer or chip. The techniques described herein include designing interconnects and forming interconnects with particular resistances.

公开(公告)号：US20220085238A1

公开(公告)日：2022-03-17

申请号：US17021391

申请日：2020-09-15

Applicant: Applied Materials, Inc.

Inventor： Michael Chudzik ,  Errol Antonio C. Sanchez

IPC: H01L33/08 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32

Abstract: Exemplary devices may include a substrate, a dielectric layer formed on the substrate, a first light source configured to emit first light characterized by a first wavelength, a second light source configured to emit second light characterized by a second wavelength different from the first wavelength, and a third light source configured to emit third light characterized by a third wavelength different from the first wavelength and the second wavelength. The first light source may be natively formed on a first region of the substrate and arranged within a first opening of the dielectric layer. The second light source may be natively formed on a second region of the substrate and arranged within a second opening of the dielectric layer. The third light source may be natively formed on a third region of the substrate and arranged within a third opening of the dielectric layer.

公开(公告)号：US11145761B2

公开(公告)日：2021-10-12

申请号：US16592362

申请日：2019-10-03

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Vanessa Pena ,  Errol Antonio C. Sanchez ,  Benjamin Colombeau ,  Michael Chudzik ,  Bingxi Wood ,  Nam Sung Kim

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US09865735B2

公开(公告)日：2018-01-09

申请号：US15152273

申请日：2016-05-11

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Vanessa Pena ,  Errol Antonio C. Sanchez ,  Benjamin Colombeau ,  Michael Chudzik ,  Bingxi Wood ,  Nam Sung Kim

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78642

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US20220319836A1

公开(公告)日：2022-10-06

申请号：US17697058

申请日：2022-03-17

Applicant: Applied Materials, Inc.

Inventor： Michael Chudzik ,  Ria Someshwar ,  Daniel Deyo ,  Michel Khoury ,  Sha Zhao

IPC: H01L21/02 ,  H01L21/033

Abstract: Exemplary processing methods include forming a nucleation layer on a substrate. The nucleation layer may be formed by physical vapor deposition (PVD), and the physical vapor deposition may be characterized by a deposition temperature of greater than or about 700° C. The methods may further include forming a patterned mask layer on the nucleation layer. The patterned mask layer may include openings that expose portions of the nucleation layer. Gallium-and-nitrogen-containing regions may be formed on the exposed portions of the nucleation layer. In additional embodiments, the nucleation layer may include a first and second portion separated by an interlayer that stop the propagation of at least some dislocations in the nucleation layer.

公开(公告)号：US20220293821A1

公开(公告)日：2022-09-15

申请号：US17197493

申请日：2021-03-10

Applicant: Applied Materials, Inc.

Inventor： Michael Chudzik ,  Michel Khoury ,  Max Batres

IPC: H01L33/32 ,  H01L33/22 ,  H01L33/00

Abstract: Exemplary processing methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. The methods may further include forming first, second, and third, gallium-and-nitrogen-containing regions on the nucleation layer. The first gallium-and-nitrogen-containing region may be porosified, without porosifying the second and third gallium-and-nitrogen containing regions. The methods may still further include forming a first active region on the porosified first gallium-and-nitrogen-containing region, and a second active region on the unporosified second gallium-and-nitrogen-containing region. The methods may yet also include forming a third active region on the unporosified third gallium- and-nitrogen-containing region.

公开(公告)号：US11322649B2

公开(公告)日：2022-05-03

申请号：US17021391

申请日：2020-09-15

Applicant: Applied Materials, Inc.

Inventor： Michael Chudzik ,  Errol Antonio C. Sanchez

IPC: H01L33/00 ,  H01L33/08 ,  H01L33/32 ,  H01L33/24 ,  H01L33/06

Abstract: Exemplary devices may include a substrate, a dielectric layer formed on the substrate, a first light source configured to emit first light characterized by a first wavelength, a second light source configured to emit second light characterized by a second wavelength different from the first wavelength, and a third light source configured to emit third light characterized by a third wavelength different from the first wavelength and the second wavelength. The first light source may be natively formed on a first region of the substrate and arranged within a first opening of the dielectric layer. The second light source may be natively formed on a second region of the substrate and arranged within a second opening of the dielectric layer. The third light source may be natively formed on a third region of the substrate and arranged within a third opening of the dielectric layer.

公开(公告)号：US11536708B2

公开(公告)日：2022-12-27

申请号：US16738629

申请日：2020-01-09

Applicant: Applied Materials, Inc.

Inventor： Mark J. Saly ,  Keenan Navarre Woods ,  Joseph R. Johnson ,  Bhaskar Jyoti Bhuyan ,  William J. Durand ,  Michael Chudzik ,  Raghav Sreenivasan ,  Roger Quon

IPC: B82Y15/00 ,  B82Y40/00 ,  G01N33/487 ,  B01D67/00 ,  C12Q1/6869

Abstract: Embodiments of the present disclosure provide dual pore sensors and methods for producing these dual pore sensors. The method includes forming a film stack, where the film stack contains two silicon layers and two membrane layers, and then etching the film stack to produce a channel extending therethrough and having two reservoirs and two nanopores. The method also includes depositing a oxide layer on inner surfaces of the reservoirs and nanopores, depositing a dielectric layer on the oxide layer, and forming a metal contact extending through a portion of the stack. The method further includes etching the dielectric layers to form wells, etching the first silicon layer to reveal the protective oxide layer deposited on the inner surfaces of a reservoir, and etching the protective oxide layer deposited on the inner surfaces of the reservoirs and the nanopores.

公开(公告)号：US11410873B2

公开(公告)日：2022-08-09

申请号：US16953567

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Tyler Sherwood ,  Michael Chudzik ,  Siddarth Krishnan

IPC: H01L29/00 ,  H01L29/94 ,  H01L31/062 ,  H01L21/768 ,  H01L29/06 ,  H01L21/762

Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.

公开(公告)号：US10573719B2

公开(公告)日：2020-02-25

申请号：US15279257

申请日：2016-09-28

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Benjamin Colombeau ,  Michael Chudzik

IPC: H01L21/76 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L29/786 ,  H01L29/15

Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.