公开(公告)号：US08012842B2

公开(公告)日：2011-09-06

申请号：US12137817

申请日：2008-06-12

申请人： Scott Balster ,  Badih El-Kareh ,  Hiroshi Yasuda

发明人： Scott Balster ,  Badih El-Kareh ,  Hiroshi Yasuda

IPC分类号： H01L21/331

CPC分类号： H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0826 ,  H01L27/1203

摘要： An integrated semiconductor structure that has first and second bipolar transistor structures. The first bipolar transistor structure has a doped tank region in contact with a doped tank region located underneath a contacting sinker. The second bipolar transistor structure has a doped buried region that is the same dopant type as its doped tank region. A method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer. A first patterned photomask is used to form a doped buried region and a doped tank region within the first bipolar transistor structure. A second patterned photomask is used to form a doped buried region and a doped tank region within the second bipolar transistor, plus a doped buried region and a doped tank region underneath a contacting sinker adjacent to the first bipolar transistor.

摘要翻译： 具有第一和第二双极晶体管结构的集成半导体结构。 第一双极晶体管结构具有与位于接触沉降片下方的掺杂槽区接触的掺杂槽区。 第二双极晶体管结构具有与其掺杂槽区相同的掺杂剂类型的掺杂掩埋区。 一种用于在体半导体晶片中制造集成半导体结构的方法。 第一图案化光掩模用于在第一双极晶体管结构内形成掺杂掩埋区和掺杂槽区。 第二图案化光掩模用于在第二双极晶体管内形成掺杂掩埋区和掺杂槽区，加上与第一双极晶体管相邻的接触沉积片下方的掺杂掩埋区和掺杂槽区。

公开(公告)号：US20070057281A1

公开(公告)日：2007-03-15

申请号：US11470760

申请日：2006-09-07

申请人： Badih El-Kareh ,  Scott Balster ,  Hiroshi Yasuda ,  Manfred Schiekofer

发明人： Badih El-Kareh ,  Scott Balster ,  Hiroshi Yasuda ,  Manfred Schiekofer

IPC分类号： H01L29/74

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0705

摘要： An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.

摘要翻译： 具有栅极自保护的集成电路包括MOS器件和双极器件，其中所述集成电路还包括具有电活性区域的半导体层，在其上形成MOS器件和双极器件，并且在其上形成用于隔离的电无活性区域 电活性区域彼此。 MOS器件包括栅极结构和体接触结构，其中所述体接触结构由沉积在所述半导体层的电活性区域上的选定区域中的基底层形成，并且所述体接触结构与所述栅极电连接 结构体。 形成身体接触结构的基层也形成双极器件的基部。 本发明还涉及一种用于制造这种集成电路的方法。

公开(公告)号：US20050118771A1

公开(公告)日：2005-06-02

申请号：US10978074

申请日：2004-10-28

申请人： Hiroshi Yasuda ,  Badih El-Kareh ,  Scott Balster ,  Manfred Schiekofer

发明人： Hiroshi Yasuda ,  Badih El-Kareh ,  Scott Balster ,  Manfred Schiekofer

IPC分类号： H01L21/331 ,  H01L29/10 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L21/425 ,  H01L21/8222

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A method of producing a vertical bipolar PNP transistor is disclosed. The phosphorous profile in the base layer is controlled. Carbon that is incorporated in the base layer in the vicinity of the base-collector junction suppresses the diffusion of phosphorous deeper than implanted in a subsequent thermal step. PNP transistors with a narrow phosphorous-doped base can thus be manufactured with a cut-off frequency increased from 23 GHz to 30 GHz.

摘要翻译： 公开了一种制造垂直双极PNP晶体管的方法。 控制基层中的磷分布。 在底部 - 集电极结附近并入基底层中的碳，抑制磷的扩散比在随后的热步骤中植入更深。 因此可以制造具有从23GHz至30GHz的截止频率的具有窄磷掺杂基极的PNP晶体管。

公开(公告)号：US08450179B2

公开(公告)日：2013-05-28

申请号：US11670729

申请日：2007-02-02

申请人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

发明人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

IPC分类号： H01L21/331

CPC分类号： H01L29/7378 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0825 ,  H01L29/66242

摘要： A method for fabricating a semiconductor device having a first and second bipolar devices of the same dopant type includes: depositing a dielectric layer over a semiconductor layer, depositing a gate conductor layer over the dielectric layer, defining base regions of both bipolar devices, removing the gate conductor layer and dielectric layer in the base regions, depositing a base layer on the gate conductor layer and on the exposed semiconductor layer in the base regions, depositing an insulating layer over the base layer, forming a photoresist layer and defining emitter regions of both bipolar devices, removing the photoresist layer in the emitter regions thereby forming two emitter windows, masking the emitter window of the first bipolar device and exposing the base layer in the base region of the second bipolar device to an additional emitter implant through the associated emitter window.

摘要翻译： 一种用于制造具有相同掺杂剂类型的第一和第二双极器件的半导体器件的方法包括：在半导体层上沉积介电层，在电介质层上沉积栅极导体层，限定两个双极器件的基极区域， 栅极导体层和电介质层，在栅极导体层和基极区域的暴露的半导体层上沉积基底层，在基底层上沉积绝缘层，形成光致抗蚀剂层并限定两者的发射极区域 去除发射极区域中的光致抗蚀剂层，从而形成两个发射器窗口，掩蔽第一双极器件的发射极窗口，并将第二双极器件的基极区域中的基极层通过相关的发射极窗口暴露于另外的发射体注入 。

公开(公告)号：US20070207585A1

公开(公告)日：2007-09-06

申请号：US11670729

申请日：2007-02-02

申请人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

发明人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Balster

IPC分类号： H01L21/331

CPC分类号： H01L29/7378 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0825 ,  H01L29/66242

摘要： A method of fabricating a BiCMOS device comprising a first bipolar device and a second bipolar device being of the same dopant type and a BiCMOS device comprising a first bipolar device and a second bipolar device being of the same dopant type A method for fabricating a BICMOS device comprising a first bipolar device and a second bipolar device being of the same dopant type comprises the steps of depositing a dielectric layer (24) over a semiconductor layer (14), depositing a gate conductor layer (26) over the dielectric layer (24), defining base regions (28, 30) of the first and second bipolar devices; removing the gate conductor layer (26) and the dielectric layer (24) in the base regions (28, 30) of the first and second bipolar devices, depositing a base layer (32) on the gate conductor layer (26) and on the exposed semiconductor layer (14) in the base regions (28, 30) of the first and second bipolar devices depositing an insulating layer (36) over said base layer (32), forming a photoresist layer (38) and defining emitter regions (40, 42) of the first and second bipolar devices, removing the photoresist layer (38) in the emitter regions (40, 42) of the first and second bipolar devices thereby forming two emitter windows (44, 46), masking the emitter window (44) of the first bipolar device and exposing said base layer (32) in the base region (30) of the second bipolar device to an additional emitter implant through the associated emitter window (46).

摘要翻译： 一种制造BiCMOS器件的方法，其包括具有相同掺杂剂类型的第一双极器件和第二双极器件，以及包括第一双极器件和第二双极器件的BiCMOS器件，其具有相同的掺杂剂A型制造BICMOS器件的方法 包括第一双极器件和具有相同掺杂剂类型的第二双极器件包括以下步骤：在半导体层（14）上沉积介电层（24），在电介质层（24）上沉积栅极导体层（26） 限定第一和第二双极器件的基极区域（28,30）; 去除第一和第二双极器件的基极区域（28,30）中的栅极导体层（26）和介电层（24），在栅极导体层（26）上沉积基极层（32） 在所述第一和第二双极器件的基极区（28,30）中暴露的半导体层（14）在所述基极层（32）上沉积绝缘层（36），形成光致抗蚀剂层（38）并限定发射极区域 ，42），去除第一和第二双极器件的发射极区域（40,42）中的光致抗蚀剂层（38），从而形成两个发射器窗口（44,46），掩蔽发射器窗口 44），并且通过所述相关联的发射器窗（46）将所述第二双极器件的基极区域（30）中的所述基极层（32）暴露于另外的发射体注入。

公开(公告)号：US20090127630A1

公开(公告)日：2009-05-21

申请号：US12137817

申请日：2008-06-12

申请人： Scott Balster ,  Badih El-Kareh ,  Hiroshi Yasuda

发明人： Scott Balster ,  Badih El-Kareh ,  Hiroshi Yasuda

IPC分类号： H01L21/265 ,  H01L27/06

CPC分类号： H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0826 ,  H01L27/1203

摘要： An integrated semiconductor structure and a method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer.

摘要翻译： 一种集成半导体结构和用于在体半导体晶片中制造集成半导体结构的方法。

公开(公告)号：US07217322B2

公开(公告)日：2007-05-15

申请号：US10934188

申请日：2004-09-02

申请人： Jeffrey A. Babcock ,  Scott Balster ,  Alfred Haeusler ,  Angelo Pinto ,  Manfred Schiekofer ,  Philipp Steinmann ,  Badih El-Kareh

发明人： Jeffrey A. Babcock ,  Scott Balster ,  Alfred Haeusler ,  Angelo Pinto ,  Manfred Schiekofer ,  Philipp Steinmann ,  Badih El-Kareh

IPC分类号： C30B25/04

CPC分类号： C23C16/42 ,  C23C16/56 ,  H01L21/02532 ,  H01L21/02576

摘要： A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.

摘要翻译： 制造用于集成半导体器件的外延硅 - 锗层的方法包括沉积砷原位掺杂硅 - 锗层的步骤，其中砷和锗随后在沉积期间被引入所述硅 - 锗层的不同区域 所述硅 - 锗层。 通过从锗中分离砷，可避免在沉积过程中砷和锗之间的相互作用，从而允许制造具有可重复掺杂分布的硅 - 锗层。

公开(公告)号：US07498639B2

公开(公告)日：2009-03-03

申请号：US11233960

申请日：2005-09-23

申请人： Philipp Steinmann ,  Scott Balster ,  Badih El-Kareh ,  Thomas Scharnagl ,  Michael Schmitt

发明人： Philipp Steinmann ,  Scott Balster ,  Badih El-Kareh ,  Thomas Scharnagl ,  Michael Schmitt

IPC分类号： H01L31/112

CPC分类号： H01L27/0623 ,  H01L21/76229 ,  H01L21/8249 ,  H01L27/0207

摘要： An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components, and has isolation trenches to separate the active moat areas from each other and from the dummy moat areas. The dummy moat areas comprise dummy window structures having geometrical dimensions and shapes similar to those of the active window structures for the base and/or emitter windows.

摘要翻译： 集成的BiCMOS半导体电路在硅中具有积极的护城河区域。 活动的护壕区域包括半导体电路的电活性部件，其包括用于基底和/或发射器窗口的有源窗口结构。 集成的BiCMOS半导体电路具有区域，其中硅留下以形成不包括电活性部件的虚拟护城河区域，并且具有隔离沟槽以将活动的护壕区域彼此分开并与虚拟的护城河区域分离。 虚拟护城河区域包括具有几何尺寸和形状的虚拟窗户结构，其类似于用于基座和/或发射器窗口的活动窗口结构的几何尺寸和形状。

公开(公告)号：US07192838B2

公开(公告)日：2007-03-20

申请号：US10928655

申请日：2004-08-26

申请人： Philipp Steinmann ,  Scott Balster ,  Badih El-Kareh ,  Thomas Scharnagl

发明人： Philipp Steinmann ,  Scott Balster ,  Badih El-Kareh ,  Thomas Scharnagl

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L21/82285 ,  H01L29/7378

摘要： Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60) is separately patterned, allowing these layers to be optimized for the respective conductivity type.

摘要翻译： 制造互补SiGe双极晶体管的方法。 在制造互补SiGe双极晶体管的方法中，分别形成用于NPN和PNP发射极（44,64）的界面氧化物层（38,58），发射极多晶硅（40,60）被分开构图，允许这些层被优化 对于各自的导电类型。

公开(公告)号：US20050014341A1

公开(公告)日：2005-01-20

申请号：US10822078

申请日：2004-04-08

申请人： Badih El-Kareh ,  Scott Balster ,  Philipp Steinmann ,  Thomas Scharnagl ,  Manfred Schiekofer ,  Carl Willis

发明人： Badih El-Kareh ,  Scott Balster ,  Philipp Steinmann ,  Thomas Scharnagl ,  Manfred Schiekofer ,  Carl Willis

IPC分类号： H01L21/331 ,  H01L21/8228

CPC分类号： H01L29/66242 ,  H01L21/82285

摘要： In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regions 20, 14 by epitaxial deposition of crystalline silicon-germanium layers 32a, 36a. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layers 32a, 36a can be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers 32a, 36a.

摘要翻译： 在制造具有SiGe基极区域的互补双极晶体管的方法中，NPN和PNP晶体管的基极区域通过晶体硅 - 锗层32a，36a的外延沉积而在两个集电极区域20,14之间一个接一个地形成。 使用这种方法，可以自由地为NPN和PNP晶体管选择SiGe层的锗分布，从而可以单独优化互补晶体管的性能。 SiGe层32a，36a可以在硅 - 锗层32a，36a沉积期间或之后掺杂n型或p型掺杂剂。