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    Early high level net based analysis of simultaneous switching
    1.
    发明授权
    Early high level net based analysis of simultaneous switching 失效
    同步切换的早期高级网络分析

    公开(公告)号：US5477460A

    公开(公告)日：1995-12-19

    申请号：US360519

    申请日：1994-12-21

    申请人： Charles K. Vakirtzis ,  George A. Katopis ,  Gerald W. Mahoney ,  Craig R. Selinger ,  Bradley D. McCredie ,  Wiren D. Becker

    发明人： Charles K. Vakirtzis ,  George A. Katopis ,  Gerald W. Mahoney ,  Craig R. Selinger ,  Bradley D. McCredie ,  Wiren D. Becker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： Switching characteristics of system components are represented and summed so that their effects on the overall system can be observed during the design process. Full simultaneous switching analysis is provided at the earliest levels of design containing minimal level of design data by a method of computing net based simultaneous switching noise levels which supports packages ranging from the smallest chip level to the largest board level. The simultaneous switching activity is computed based on interaction between each driver and each other driver between each component and each other component, with consideration to the spatial inter-relationship net, within a higher level component, to determine each component's drivers effect on itself as well as the coupling effect between drivers on different components. The analysis involves computing simultaneous switching noise by associating a characteristic triangle with each driver application configuration. The characteristic triangle. The height of the triangle, as well as the pitch of the sides of the triangle will be determined by the characteristics of the net. In the early stages of design, a default characteristic triangle is defined for each technology type. A general triangle is also defined for cases where early analysis needs to be performed prior to choosing a technology.

    摘要翻译： 系统组件的开关特性被表示和相加，以便在设计过程中可以观察到它们对整个系统的影响。 通过计算基于网络的同步开关噪声电平的方法，提供了最初设计的包含最小级别的设计数据的全面同步开关分析，该方法支持从最小芯片级到最大板级的封装。 基于每个组件和每个其他组件之间的每个驱动程序和每个其他驱动程序之间的相互作用计算同时切换活动，考虑到较高级组件内的空间相互关系网，以确定每个组件的驱动程序对其本身的影响 作为不同组件上的驱动程序之间的耦合效应。 分析涉及通过将特征三角形与每个驱动程序应用程序配置相关联来计算同时切换噪声。 特征三角形。 三角形的高度以及三角形边的间距将由网络的特性决定。 在设计的早期阶段，为每种技术类型定义默认特征三角形。 对于在选择技术之前需要进行早期分析的情况，也定义了一般三角形。

    Method for dynamic bandwidth testing
    8.
    发明授权
    Method for dynamic bandwidth testing 失效
    动态带宽测试方法

    公开(公告)号：US5970052A

    公开(公告)日：1999-10-19

    申请号：US933574

    申请日：1997-09-19

    申请人： Tin-Chee Lo ,  George A. Katopis ,  Timothy Gerard McNamara ,  David Allan Webber ,  Joseph L. Braun ,  Paul R. Turgeon

    发明人： Tin-Chee Lo ,  George A. Katopis ,  Timothy Gerard McNamara ,  David Allan Webber ,  Joseph L. Braun ,  Paul R. Turgeon

    IPC分类号： G01R31/3173 ,  G06F11/267

    CPC分类号： G06F11/221 ,  G01R31/3173

    摘要： A method for dynamic bandwidth testing of a link between two computer subsystems useful for determining the amount of data which can be buffered in a transmission line by delay, in which at each end of the line circuit modules are provided to couple the subsystem by a bi-directional multi-bit (BiDi) link, and providing within each said circuit module a built-in circuit and logic for dynamic transmission characterization and test of a said BiDi link between computer subsystems using built-in characterization logic macros, and during a test mode, switching said said built-in circuit and logic to test mode and using the test mode to characterize the link performance, and after the completion of characterization, the switching built-in characterization logic macros back to a normal system mode after programmatically setting timing parameters for the BiDi link to ensure safe operation of data transfer before the BiDi link is switched to system mode.

    摘要翻译： 一种用于在两个计算机子系统之间的链路的动态带宽测试的方法，其用于确定可以通过延迟在传输线路中缓冲的数据量，其中在线路电路模块的每一端被提供以通过bi耦合子系统 并且在每个所述电路模块内提供内置电路和逻辑，用于使用内置的表征逻辑宏以及在测试期间对计算机子系统之间的所述BiDi链路进行动态传输表征和测试 模式，将所述内置电路和逻辑切换到测试模式并使用测试模式来表征链路性能，并且在表征完成之后，通过编程设置定时将交换内置表征逻辑宏恢复到正常的系统模式 BiDi链路的参数，以确保在BiDi链路切换到系统模式之前数据传输的安全运行。

    On-chip Delta-I noise clamping circuit
    9.
    发明授权
    On-chip Delta-I noise clamping circuit 失效
    片上Delta-I噪声钳位电路

    公开(公告)号：US4398106A

    公开(公告)日：1983-08-09

    申请号：US218150

    申请日：1980-12-19

    申请人： Evan E. Davidson ,  George A. Katopis ,  Barry J. Rubin

    发明人： Evan E. Davidson ,  George A. Katopis ,  Barry J. Rubin

    IPC分类号： H03K19/0175 ,  G05F1/46 ,  H01L27/00 ,  H01L27/01 ,  H04B15/00 ,  H04L25/08 ,  H03H11/46 ,  H03H5/12

    CPC分类号： G05F1/467

    摘要： A clamping circuit to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips and the chips have a power supply and power leads respectively. An impedance path is defined between each of the chips and the power supply to define a current path for switching noise through the top of the module. A high impedance path is defined for voltages below a predetermined upper limit of the chip supply voltage and a low impedance path is defined by the clamping circuit for the voltage range where noise superimposed on the chip supply voltage occurs.

    摘要翻译： 一种用于在多芯片模块半导体结构中减少自感应开关噪声的钳位电路。 模块部分互连芯片，芯片分别具有电源和电源引线。 在每个芯片和电源之间限定阻抗路径，以限定用于通过模块顶部切换噪声的电流路径。 对于低于芯片电源电压的预定上限的电压，限定高阻抗路径，并且在钳位电路中限定出叠加在芯片电源电压上的噪声的电压范围的低阻抗路径。