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公开(公告)号：US11031076B2
公开(公告)日：2021-06-08
申请号：US16684987
申请日：2019-11-15
IPC分类号： G11C11/419 , G11C11/00 , G11C11/412
摘要： A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns, the cells of a same column sharing a same read bit line and a same write bit line; an internal control circuit capable of implementing a calculation operation including the simultaneous activation in read mode of at least two rows of the array; and a shuffle circuit including a data input register, a configuration register, and an output port, the shuffle circuit being capable of delivering on its output port the data stored in its input register shuffled according to a shuffle operation defined according to the state of its configuration register.
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公开(公告)号：US09479168B2
公开(公告)日：2016-10-25
申请号：US14225520
申请日：2014-03-26
申请人： Commissariat à l'énergie atomique et aux énergies alternatives , STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
发明人： Bastien Giraud , Fady Abouzeid , Sylvain Clerc , Jean-Philippe Noel , Philippe Roche , Yvain Thonnart
IPC分类号： H03K19/096 , H03K19/00 , H01L27/092 , H01L27/118 , H01L27/12 , H03K19/0185
CPC分类号： H03K19/0016 , H01L27/0928 , H01L27/11807 , H01L27/1203 , H03K19/0013 , H03K19/01855 , H03K2217/0018
摘要： A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.
摘要翻译： 一种用于控制具有逻辑单元和时钟树单元的IC的方法。 每个逻辑单元分别具有第一和第二FET，分别是pMOS和nMOS。 时钟树单元包括分别为pMOS和nMOS的第三和第四FET。 时钟树单元为逻辑单元提供时钟信号。 pMOS-FET的背栅电位差（“BGPD”）是其源电位减去其背栅电位之间的差异，反之亦然是nMOS-FET。 该方法包括将第一和第二后门电位差（BGPD）应用于逻辑单元的第一和第二FET，以及将第三BGPD应用于第三FET，其中第三BGPD为正并且大于施加的第一BGPD，其被应用 同时或将第四BGEPD应用于第四FET，其中第四BGPD为正并且大于并发应用的第二BGPD。
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3.发明申请公开(公告)号：US20150287722A1
公开(公告)日：2015-10-08
申请号：US14435004
申请日：2013-10-11
IPC分类号： H01L27/092 , H01L27/12
CPC分类号： H01L27/092 , H01L21/823892 , H01L27/1203
摘要： An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.
摘要翻译： 集成电路包括具有第一和第二单元的衬底，第一和第二单元具有第一和第二FDSOI场效应晶体管。 在地平面下方有第一和第二接地层，一个埋置的氧化物层和一个和第二个井。 第一阱和第一接地层具有相同的掺杂，第二阱和第二接地层具有相同的掺杂。 第一和第二单元相邻并且它们的晶体管沿第一方向排列。 第一单元的阱和第二单元的第一阱与第二阱相反地掺杂。 控制装置利用第一掺杂将第一电偏压施加到阱，并且通过第二掺杂向阱施加第二电偏压。 第一单元和第二单元的晶体管具有不同的阈值电压电平。
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公开(公告)号：US20230047801A1
公开(公告)日：2023-02-16
申请号：US17796841
申请日：2021-02-05
IPC分类号： G06F3/06
摘要： A method of circuit conception of a computational memory circuit including a memory having memory cells, the method including: receiving an indication of the memory storage size and an indication of an instruction frequency of the instructions to be executed by the computational memory circuit; evaluating for a plurality of candidate types of memory cells, a number representing an average number of cycles of the memory of the computational memory circuit per instruction to be executed; determining, for each of the plurality of candidate types of memory cells, a minimum operating frequency of the computational memory circuit based on the number N and on the memory storage size; selecting one of the plurality of candidate types of memory cells based on the determined minimum operating frequency; and performing the circuit conception based on the selected type of candidate memory cell.
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公开(公告)号：US10811087B2
公开(公告)日：2020-10-20
申请号：US16224741
申请日：2018-12-18
发明人： Jean-Philippe Noel , Bastien Giraud
IPC分类号： G11C11/419 , G11C7/10 , G11C11/417 , G11C11/412
摘要： A memory circuit including a plurality of elementary cells arranged in an array of rows and of columns, and a control circuit capable of implementing an operation of vertical reading of a word from a column of the array.
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公开(公告)号：US20200160905A1
公开(公告)日：2020-05-21
申请号：US16684987
申请日：2019-11-15
IPC分类号： G11C11/419 , G11C11/412 , G11C11/00
摘要： A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns, the cells of a same column sharing a same read bit line and a same write bit line; an internal control circuit capable of implementing a calculation operation including the simultaneous activation in read mode of at least two rows of the array; and a shuffle circuit including a data input register, a configuration register, and an output port, the shuffle circuit being capable of delivering on its output port the data stored in its input register shuffled according to a shuffle operation defined according to the state of its configuration register.
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公开(公告)号：US10043581B2
公开(公告)日：2018-08-07
申请号：US15603284
申请日：2017-05-23
发明人： Jean-Philippe Noel , Kaya Can Akyel
IPC分类号： G06F17/30 , G11C16/10 , G11C14/00 , G11C16/24 , G11C7/10 , G11C11/417 , G11C11/412
摘要： A memory circuit capable of implementing calculation operations, including: memory cells arranged in rows and in columns, each cell including: a data bit storage node, a read-out transistor connected by its gate to the storage node, and a selection transistor series-connected with the read-out transistor between a reference node and a conductive output track common to all the cells of a same column; and a control circuit configured to simultaneously activate the selection transistors of at least two cells of a same column of the circuit, and to read from the conductive output track of the column a value representative of the result of a logic operation having as operands the data of the two cells.
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公开(公告)号：US20140292374A1
公开(公告)日：2014-10-02
申请号：US14225520
申请日：2014-03-26
申请人： Commissariat à l'énergie atomique et aux énergies alternatives , STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
发明人： Bastien Giraud , Fady Abouzeid , Sylvain Clerc , Jean-Philippe Noel , Philippe Roche , Yvain Thonnart
IPC分类号： H03K19/00 , H03K19/0185
CPC分类号： H03K19/0016 , H01L27/0928 , H01L27/11807 , H01L27/1203 , H03K19/0013 , H03K19/01855 , H03K2217/0018
摘要： A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.
摘要翻译： 一种用于控制具有逻辑单元和时钟树单元的IC的方法。 每个逻辑单元分别具有第一和第二FET，分别是pMOS和nMOS。 时钟树单元包括分别为pMOS和nMOS的第三和第四FET。 时钟树单元为逻辑单元提供时钟信号。 pMOS-FET的背栅电位差（“BGPD”）是其源电位减去其背栅电位之间的差异，反之亦然是nMOS-FET。 该方法包括将第一和第二后门电位差（BGPD）应用于逻辑单元的第一和第二FET，以及将第三BGPD应用于第三FET，其中第三BGPD为正并且大于施加的第一BGPD，其被应用 同时或将第四BGEPD应用于第四FET，其中第四BGPD为正并且大于并发应用的第二BGPD。
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公开(公告)号：US10910040B2
公开(公告)日：2021-02-02
申请号：US16231248
申请日：2018-12-21
IPC分类号： G11C11/00 , G11C11/419 , G11C13/00 , G11C7/10 , G11C11/412 , G11C7/18 , G11C11/417 , G11C5/06 , G11C5/02 , H03K19/177 , G11C11/407 , G11C11/408 , G11C11/4097 , G11C11/4094 , G11C8/12 , G11C11/405 , G11C11/4096
摘要： A memory circuit including a plurality of elementary cells arranged in a plurality of arrays, each including a plurality of rows and a plurality of columns, and wherein: the elementary cells having the same coordinates in the different arrays share a same first conductive track; and in each array, the elementary cells of a same row of the array share a same second conductive track and a same third conductive track.
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公开(公告)号：US20190198094A1
公开(公告)日：2019-06-27
申请号：US16231248
申请日：2018-12-21
IPC分类号： G11C11/419 , G11C13/00
CPC分类号： G11C11/419 , G11C5/025 , G11C5/063 , G11C7/1006 , G11C7/1066 , G11C7/1069 , G11C7/1093 , G11C7/1096 , G11C7/18 , G11C8/12 , G11C11/405 , G11C11/407 , G11C11/4085 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C11/412 , G11C11/417 , G11C13/003 , G11C13/004 , G11C13/0069 , H03K19/177
摘要： A memory circuit including a plurality of elementary cells arranged in a plurality of arrays, each including a plurality of rows and a plurality of columns, and wherein: the elementary cells having the same coordinates in the different arrays share a same first conductive track; and in each array, the elementary cells of a same row of the array share a same second conductive track and a same third conductive track.
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