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公开(公告)号：US07344318B2
公开(公告)日：2008-03-18
申请号：US11386149
申请日：2006-03-22
申请人： Daoqiang Lu , Henning Braunisch , Bram Leader , Mark B. Trobough
发明人： Daoqiang Lu , Henning Braunisch , Bram Leader , Mark B. Trobough
CPC分类号： G02B6/4292 , G02B6/3885 , G02B6/423 , H01L2224/16225
摘要： A coupler is passively aligned over a substrate, wherein the coupler is laterally aligned to an optoelectronic (OE) device coupled to the substrate. The coupler is placed on the substrate, wherein the coupler is vertically aligned to the OE device. The coupler is fixed to the substrate.
摘要翻译： 耦合器在衬底上被动对准，其中耦合器横向对准耦合到衬底的光电子（OE）器件。 耦合器被放置在基板上，其中耦合器垂直对准OE设备。 耦合器固定在基板上。
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公开(公告)号：US20150127983A1
公开(公告)日：2015-05-07
申请号：US13997182
申请日：2010-12-23
申请人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
发明人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
IPC分类号： G06F11/273
CPC分类号： G06F11/2733 , G06F11/267
摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
摘要翻译： 这里描述了一种用于提供测试，验证和调试架构的装置和方法。 在目标或基础级别，硬件（测试设计或DFx）被设计并集成在硅部件中。 控制器可以提供对这种钩子的抽象访问，例如通过抽象层来抽象硬件DFx的低级细节。 此外，通过接口（如API）的抽象层向更高级的软件/表示层提供服务，例程和数据结构，这些层能够收集测试数据，以便对被测单元/平台进行验证和调试。 此外，该架构可能提供对测试架构的分层（多级）安全访问。 此外，可以通过使用统一的双向测试访问端口来简化对平台的测试架构的物理访问，同时还可能允许远程访问执行被测部件/平台的远程测试和脱离。 本质上描述了一个完整的测试架构栈，用于电子部件，设备和平台的测试，验证和调试。
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公开(公告)号：US20120322314A1
公开(公告)日：2012-12-20
申请号：US13468618
申请日：2012-05-10
IPC分类号： H01R24/76
CPC分类号： H01L22/14 , G01R1/0483 , H01L22/32 , H01L23/49838 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.
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4.发明授权公开(公告)号：US08212350B2
公开(公告)日：2012-07-03
申请号：US12384634
申请日：2009-04-06
IPC分类号： H01L23/48
CPC分类号： H01L22/14 , G01R1/0483 , H01L22/32 , H01L23/49838 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，集成电路封装包括多个系统功能引脚，至少一个系统功能引脚释放区，以及至少一个非系统功能引脚，位于该至少一个功能引脚销毁区中。 描述和要求保护其他实施例。
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5.发明授权公开(公告)号：US08834184B2
公开(公告)日：2014-09-16
申请号：US13468618
申请日：2012-05-10
IPC分类号： H01R12/00 , H05K1/00 , H01L23/498 , G01R1/04
CPC分类号： H01L22/14 , G01R1/0483 , H01L22/32 , H01L23/49838 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，集成电路封装包括多个系统功能引脚，至少一个系统功能引脚释放区，以及至少一个非系统功能引脚，位于该至少一个功能引脚销毁区中。 描述和要求保护其他实施例。
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公开(公告)号：US06971887B1
公开(公告)日：2005-12-06
申请号：US10877323
申请日：2004-06-24
申请人： Mark B. Trobough
发明人： Mark B. Trobough
CPC分类号： H05K7/1092
摘要： A multi-portion socket, related components, and systems having such socket/components are described herein.
摘要翻译： 这里描述了具有这种插座/部件的多部分插座，相关组件和系统。
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公开(公告)号：US5603619A
公开(公告)日：1997-02-18
申请号：US504842
申请日：1995-07-20
IPC分类号： G01R1/04 , G01R31/28 , H01R12/62 , H01R12/71 , H01R13/24 , H01R13/6471 , H01R13/66 , H01R13/719 , H05K3/32 , H05K3/36 , H01R9/09
CPC分类号： H01R12/62 , G01R1/04 , G01R31/2818 , H01R12/714 , H01R13/6471 , H01R13/6658 , H01R13/719 , H01R13/24 , H05K3/325 , H05K3/361
摘要： An apparatus for electrically connecting electrical contact pads on a first circuit board to electrical contact pads on a second circuit board is disclosed. Conductive bumps coupled to signal wires on a support element mate with the electrical contact pads on the first and second circuit boards. The mating provides an electrical connection allowing signals to be transmitted between the circuit boards. Alignment holes and alignment circuitry provide a means for verifying that the proper conductive bumps are mating with the proper electrical contact pads.
摘要翻译： 公开了一种用于将第一电路板上的电接触焊盘电连接到第二电路板上的电接触焊盘的装置。 耦合到支撑元件上的信号线的导电凸块与第一和第二电路板上的电接触焊盘配合。 配合提供电连接，允许信号在电路板之间传输。 对准孔和对准电路提供了用于验证适当的导电凸块与适当的电接触垫相配合的装置。
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8.发明授权公开(公告)号：US09111927B2
公开(公告)日：2015-08-18
申请号：US13493129
申请日：2012-06-11
IPC分类号： H01L23/48 , H01L23/498 , G01R1/04
CPC分类号： H01L22/14 , G01R1/0483 , H01L22/32 , H01L23/49838 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，集成电路封装包括多个系统功能引脚，至少一个系统功能引脚释放区，以及至少一个非系统功能引脚，位于该至少一个功能引脚销毁区中。 描述和要求保护其他实施例。
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9.发明申请公开(公告)号：US20100252920A1
公开(公告)日：2010-10-07
申请号：US12384634
申请日：2009-04-06
CPC分类号： H01L22/14 , G01R1/0483 , H01L22/32 , H01L23/49838 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，集成电路封装包括多个系统功能引脚，至少一个系统功能引脚释放区，以及至少一个非系统功能引脚，位于该至少一个功能引脚销毁区中。 描述和要求保护其他实施例。
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公开(公告)号：US07248036B2
公开(公告)日：2007-07-24
申请号：US10857653
申请日：2004-05-27
申请人： Mark B. Trobough , Richard Glass
发明人： Mark B. Trobough , Richard Glass
IPC分类号： G01R31/28
CPC分类号： G01R31/31905 , G01R31/2889
摘要： An assembly including a processor socket having a cut region. The assemble further including a probe board having a repeater positioned in alignment with the cut region. The repeater is to receive at least a first signal. The repeater is to tap the first signal. The tapped first signal is to be transmitted to a first device. The repeater is also to reinject the first signal, and the reinjected first signal to be transmitted to a processor.
摘要翻译： 一种组件，包括具有切割区域的处理器插座。 组装还包括具有定位成与切割区域对准的中继器的探针板。 中继器至少接收第一个信号。 中继器是点击第一个信号。 点击的第一信号将被发送到第一设备。 中继器还将重新注入第一个信号，并重新注入要发送到处理器的第一个信号。
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