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    GRAPHICS PROCESSING DISPATCH FROM USER MODE
    3.
    发明申请
    GRAPHICS PROCESSING DISPATCH FROM USER MODE 有权
    图形处理从用户模式进行分配

    公开(公告)号：US20120188258A1

    公开(公告)日：2012-07-26

    申请号：US13289304

    申请日：2011-11-04

    申请人： Rex MCCRARY ,  Michael Houston ,  Philip J. Rogers ,  Gongxian Jeffrey Cheng ,  Mark Hummel ,  Paul Blinzer

    发明人： Rex MCCRARY ,  Michael Houston ,  Philip J. Rogers ,  Gongxian Jeffrey Cheng ,  Mark Hummel ,  Paul Blinzer

    IPC分类号： G06F15/16

    CPC分类号： G06F9/545 ,  G06F9/544

    摘要： A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.

    摘要翻译： 公开了一种方法，系统和计算机程序产品，用于提供对用户模式应用的加速处理设备计算资源的改进访问。 所公开的功能允许用户模式应用程序向加速处理设备提供命令，而不需要内核模式转换以便访问统一的环形缓冲区。 相反，应用程序各自提供有自己的缓冲区，加速处理设备硬件可以访问进程命令。 通过完整的操作系统支持，用户模式应用程序能够以与CPU相同的方式利用加速处理设备。

    Graphics processing dispatch from user mode
    4.
    发明授权
    Graphics processing dispatch from user mode 有权
    图形处理从用户模式调度

    公开(公告)号：US09176795B2

    公开(公告)日：2015-11-03

    申请号：US13289304

    申请日：2011-11-04

    申请人： Rex McCrary ,  Michael Houston ,  Philip J. Rogers ,  Gongxian Jeffrey Cheng ,  Mark Hummel ,  Paul Blinzer

    发明人： Rex McCrary ,  Michael Houston ,  Philip J. Rogers ,  Gongxian Jeffrey Cheng ,  Mark Hummel ,  Paul Blinzer

    IPC分类号： G06T1/00 ,  G06T15/00 ,  G06F9/46 ,  G06F9/54

    CPC分类号： G06F9/545 ,  G06F9/544

    摘要： A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.

    摘要翻译： 公开了一种方法，系统和计算机程序产品，用于提供对用户模式应用的加速处理设备计算资源的改进访问。 所公开的功能允许用户模式应用程序向加速处理设备提供命令，而不需要内核模式转换以便访问统一的环形缓冲区。 相反，应用程序各自提供有自己的缓冲区，加速处理设备硬件可以访问进程命令。 通过完整的操作系统支持，用户模式应用程序能够以与CPU相同的方式利用加速处理设备。

    Device discovery and topology reporting in a combined CPU/GPU architecture system
    7.
    发明授权
    Device discovery and topology reporting in a combined CPU/GPU architecture system 有权
    组合CPU / GPU架构系统中的设备发现和拓扑报告

    公开(公告)号：US08797332B2

    公开(公告)日：2014-08-05

    申请号：US13325824

    申请日：2011-12-14

    申请人： Paul Blinzer ,  Leendert Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Woller ,  Arshad Rahman

    发明人： Paul Blinzer ,  Leendert Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Woller ,  Arshad Rahman

    IPC分类号： G06F15/00 ,  G06T1/00 ,  G06F15/16 ,  G06T1/60

    CPC分类号： G06T1/20 ,  G06F9/30003

    摘要： Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.

    摘要翻译： 提供了作为组合的CPU / APD架构系统的一个方面的方法和装置，用于发现和报告与有效地调度和分发计算任务到组合的CPU / APD架构的各种计算资源相关的设备和系统拓扑的属性 系统。 组合的CPU / APD架构将CPU和APD统一在灵活的计算环境中。 在一些实施例中，组合的CPU / APD架构能力在单个集成电路中实现，其单元可以包括一个或多个CPU核心和一个或多个APD核心。 组合的CPU / APD架构创建了可以构建现有和新的编程框架，语言和工具的基础。

    Course grain command buffer
    8.
    发明授权
    Course grain command buffer 有权
    课程粒度命令缓冲区

    公开(公告)号：US08743131B2

    公开(公告)日：2014-06-03

    申请号：US12878519

    申请日：2010-09-09

    申请人： Rex McCrary ,  Frank Liljeros ,  Gongxian Jeffrey Cheng

    发明人： Rex McCrary ,  Frank Liljeros ,  Gongxian Jeffrey Cheng

    IPC分类号： G06T1/20

    CPC分类号： G06F9/4881 ,  G06F9/461 ,  G09G5/001 ,  G09G5/363 ,  G09G2360/12 ,  G09G2370/10

    摘要： A method for executing processes within a computer system is provided. The method includes determining when to switch from a first process, executing within the computer system, to executing another process. Execution of the first process corresponds to a computer system storage location. The method also includes switching to executing the other process based upon a time quantum and resuming execution of the first process after the time quantum has lapsed, the resuming corresponding to the storage location.

    摘要翻译： 提供了一种用于在计算机系统内执行处理的方法。 该方法包括确定何时从在计算机系统内执行的第一进程切换到执行另一进程。 第一进程的执行对应于计算机系统存储位置。 该方法还包括：在时间量过去之后基于时间量化和恢复执行第一处理切换到执行其他进程，对应于存储位置的恢复。

    Infrastructure Support for Accelerated Processing Device Memory Paging Without Operating System Integration
    9.
    发明申请
    Infrastructure Support for Accelerated Processing Device Memory Paging Without Operating System Integration 有权
    基础设施支持加速处理设备内存寻呼，无需操作系统集成

    公开(公告)号：US20130159664A1

    公开(公告)日：2013-06-20

    申请号：US13325282

    申请日：2011-12-14

    申请人： Paul BLINZER ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

    发明人： Paul BLINZER ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1009 ,  G06F9/3004 ,  G06F9/3881 ,  G06F12/1081 ,  G06F2009/3883 ,  G06F2212/683

    摘要： In a CPU of the combined CPU/APD architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to an APD, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.

    摘要翻译： 在组合的CPU / APD架构系统的CPU中，CPU具有多个CPU内核，每个核具有用于接收物理页表/页目录基地址的第一机器特定寄存器，用于接收物理地址指向 到由通信地耦合到APD的IOMMUv2控制的位置，以及当被执行时导致向包含在第二机器特定寄存器中的物理地址发出写入通知的微代码; 在CPU核心的第一机器特定寄存器中接收物理页表/页目录基地址，在CPU核心的第二机器特定寄存器中接收指向由IOMMUv2控制的位置的物理地址，确定控制 已经更新了CPU核心的寄存器，并且响应于控制寄存器被更新的确定，执行CPU核心中的微代码，使得向第二机器特定寄存器中包含的物理地址发出写入通知，其中， 物理地址能够接收影响IOMMUv2页表无效的写入。

    Infrastructure support for accelerated processing device memory paging without operating system integration
    10.
    发明授权
    Infrastructure support for accelerated processing device memory paging without operating system integration 有权
    基础架构支持加速处理设备内存分页，无需操作系统集成

    公开(公告)号：US08578129B2

    公开(公告)日：2013-11-05

    申请号：US13325282

    申请日：2011-12-14

    申请人： Paul Blinzer ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

    发明人： Paul Blinzer ,  Leendert Peter Van Doorn ,  Gongxian Jeffrey Cheng ,  Elene Terry ,  Thomas Roy Woller ,  Arshad Rahman

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1009 ,  G06F9/3004 ,  G06F9/3881 ,  G06F12/1081 ,  G06F2009/3883 ,  G06F2212/683

    摘要： In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.

    摘要翻译： 在CPU中，具有多个CPU核心的CPU，每个核心具有第一机器特定寄存器，第二机器特定寄存器和微代码，当被执行时，将对包含在第二机器特定寄存器中的物理地址发出写入通知; 在CPU核心的第一机器特定寄存器中接收物理页表/页目录基地址，在CPU核心的第二机器特定寄存器中接收指向由IOMMUv2控制的位置的物理地址，确定控制 已经更新了CPU核心的寄存器，并且响应于控制寄存器被更新的确定，执行CPU核心中的微代码，使得向第二机器特定寄存器中包含的物理地址发出写入通知，其中， 物理地址能够接收影响IOMMUv2页表无效的写入。