公开(公告)号：US08868889B2

公开(公告)日：2014-10-21

申请号：US12976045

申请日：2010-12-22

申请人： Deepak Mital ,  Te Khac Ma ,  Narender Vangati ,  William Burroughs

发明人： Deepak Mital ,  Te Khac Ma ,  Narender Vangati ,  William Burroughs

IPC分类号： G06F9/38 ,  G06F15/167 ,  H04L12/873

CPC分类号： G06F15/167 ,  G06F9/3851 ,  G06F9/3885 ,  H04L47/522

摘要： Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate threads of contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes instructions corresponding to threads received from the scheduler. The multi-thread instruction engine executes instructions by fetching an instruction of the thread from an instruction memory of the packet classifier and determining whether a breakpoint mode of the network processor is enabled. If the breakpoint mode is enabled, and breakpoint indicator of the fetched instruction is set, the packet classifier enters a breakpoint mode. Otherwise, if the breakpoint indicator of the fetched instruction is not set, the multi-thread instruction engine executes the fetched instruction.

摘要翻译： 描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。 分组分类器包括调度器，用于从网络处理器的多个处理模块生成对应于由分组分类器接收到的任务的上下文的线程。 多线程指令引擎处理与从调度程序接收到的线程相对应的指令。 多线程指令引擎通过从分组分类器的指令存储器取出线程的指令来执行指令，并且确定是否使能网络处理器的断点模式。 如果断点模式被使能，并且获取的指令的断点指示器被设置，则分组分类器进入断点模式。 否则，如果未设置获取的指令的断点指示符，则多线程指令引擎执行读取的指令。

公开(公告)号：US08505013B2

公开(公告)日：2013-08-06

申请号：US12975823

申请日：2010-12-22

申请人： Steven Pollock ,  William Burroughs ,  Deepak Mital ,  Te Khac Ma ,  Narender Vangati ,  Larry King

发明人： Steven Pollock ,  William Burroughs ,  Deepak Mital ,  Te Khac Ma ,  Narender Vangati ,  Larry King

IPC分类号： G06F9/46 ,  G06F12/06

CPC分类号： G06F15/167 ,  G06F9/32 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/46 ,  G06F12/10 ,  H04L12/56 ,  H04L47/2441

摘要： Described embodiments provide address translation for data stored in at least one shared memory of a network processor. A processing module of the network processor generates tasks corresponding to each of a plurality of received packets. A packet classifier generates contexts for each task, each context associated with a thread of instructions to apply to the corresponding packet. A first subset of instructions is stored in a tree memory within the at least one shared memory. A second subset of instructions is stored in a cache within a multi-thread engine of the packet classifier. The multi-thread engine maintains status indicators corresponding to the first and second subsets of instructions within the cache and the tree memory and, based on the status indicators, accesses a lookup table while processing a thread to translate between an instruction number and a physical address of the instruction in the first and second subset of instructions.

摘要翻译： 描述的实施例为存储在网络处理器的至少一个共享存储器中的数据提供地址转换。 网络处理器的处理模块生成与多个接收到的分组中的每一个对应的任务。 分组分类器为每个任务生成上下文，每个上下文与指令线程相关联以应用于相应的分组。 指令的第一子集被存储在所述至少一个共享存储器内的树存储器中。 指令的第二子集存储在分组分类器的多线程引擎内的高速缓存中。 多线程引擎保持与高速缓存和树存储器中的第一和第二指令子集相对应的状态指示符，并且基于状态指示符，在处理线程以在指令数和物理地址之间转换时，访问查找表 在指令的第一和第二子集中的指令。

公开(公告)号：US20110225394A1

公开(公告)日：2011-09-15

申请号：US12976045

申请日：2010-12-22

申请人： Deepak Mital ,  Te Khac Ma ,  Narender Vangati ,  William Burroughs

发明人： Deepak Mital ,  Te Khac Ma ,  Narender Vangati ,  William Burroughs

IPC分类号： G06F9/312

CPC分类号： G06F15/167 ,  G06F9/3851 ,  G06F9/3885 ,  H04L47/522

摘要： Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate threads of contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes instructions corresponding to threads received from the scheduler. The multi-thread instruction engine executes instructions by fetching an instruction of the thread from an instruction memory of the packet classifier and determining whether a breakpoint mode of the network processor is enabled. If the breakpoint mode is enabled, and breakpoint indicator of the fetched instruction is set, the packet classifier enters a breakpoint mode. Otherwise, if the breakpoint indicator of the fetched instruction is not set, the multi-thread instruction engine executes the fetched instruction.

摘要翻译： 描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。 分组分类器包括调度器，用于从网络处理器的多个处理模块生成对应于由分组分类器接收到的任务的上下文的线程。 多线程指令引擎处理与从调度程序接收到的线程相对应的指令。 多线程指令引擎通过从分组分类器的指令存储器取出线程的指令来执行指令，并且确定是否使能网络处理器的断点模式。 如果断点模式被使能，并且获取的指令的断点指示符被设置，则分组分类器进入断点模式。 否则，如果未设置获取的指令的断点指示符，则多线程指令引擎执行读取的指令。

公开(公告)号：US20110225588A1

公开(公告)日：2011-09-15

申请号：US12975823

申请日：2010-12-22

申请人： Steven Pollock ,  William Burroughs ,  Deepak Mital ,  Te Khac Ma ,  Narender Vangati ,  Larry King

发明人： Steven Pollock ,  William Burroughs ,  Deepak Mital ,  Te Khac Ma ,  Narender Vangati ,  Larry King

IPC分类号： G06F9/46

CPC分类号： G06F15/167 ,  G06F9/32 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/46 ,  G06F12/10 ,  H04L12/56 ,  H04L47/2441

摘要： Described embodiments provide address translation for data stored in at least one shared memory of a network processor. A processing module of the network processor generates tasks corresponding to each of a plurality of received packets. A packet classifier generates contexts for each task, each context associated with a thread of instructions to apply to the corresponding packet. A first subset of instructions is stored in a tree memory within the at least one shared memory. A second subset of instructions is stored in a cache within a multi-thread engine of the packet classifier. The multi-thread engine maintains status indicators corresponding to the first and second subsets of instructions within the cache and the tree memory and, based on the status indicators, accesses a lookup table while processing a thread to translate between an instruction number and a physical address of the instruction in the first and second subset of instructions.

摘要翻译： 描述的实施例为存储在网络处理器的至少一个共享存储器中的数据提供地址转换。 网络处理器的处理模块生成与多个接收到的分组中的每一个对应的任务。 分组分类器为每个任务生成上下文，每个上下文与指令线程相关联以应用于相应的分组。 指令的第一子集被存储在所述至少一个共享存储器内的树存储器中。 指令的第二子集存储在分组分类器的多线程引擎内的高速缓存中。 多线程引擎保持与高速缓存和树存储器中的第一和第二指令子集相对应的状态指示符，并且基于状态指示符，在处理线程以在指令数和物理地址之间转换时，访问查找表 在指令的第一和第二子集中的指令。

公开(公告)号：US20170192921A1

公开(公告)日：2017-07-06

申请号：US14987676

申请日：2016-01-04

申请人： Ren Wang ,  Yipeng Wang ,  Andrew J. Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs

发明人： Ren Wang ,  Yipeng Wang ,  Andrew J. Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs

IPC分类号： G06F13/37 ,  G06F13/16 ,  G06F12/08

CPC分类号： G06F13/37 ,  G06F9/3004 ,  G06F9/46 ,  G06F12/04 ,  G06F12/0811 ,  G06F12/0868 ,  G06F13/1642 ,  G06F13/1673 ,  G06F2212/283 ,  G06F2212/6046

摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

公开(公告)号：US20170286337A1

公开(公告)日：2017-10-05

申请号：US15087154

申请日：2016-03-31

申请人： Ren Wang ,  Yipeng Wang ,  Jr-Shian Tsai ,  Andrew Herdrich ,  Tsung-Yuan Tai ,  Niall McDonnell ,  Stephen Van Doren ,  David Sonnier ,  Debra Bernstein ,  Hugh Wilkinson ,  Narender Vangati ,  Stephen Miller ,  Gage Eads ,  Andrew Cunningham ,  Jonathan Kenny ,  Bruce Richardson ,  William Burroughs ,  Joseph Hasting ,  An Yan ,  James Clee ,  Te Ma ,  Jerry Pirog ,  Jamison Whitesell

发明人： Ren Wang ,  Yipeng Wang ,  Jr-Shian Tsai ,  Andrew Herdrich ,  Tsung-Yuan Tai ,  Niall McDonnell ,  Stephen Van Doren ,  David Sonnier ,  Debra Bernstein ,  Hugh Wilkinson ,  Narender Vangati ,  Stephen Miller ,  Gage Eads ,  Andrew Cunningham ,  Jonathan Kenny ,  Bruce Richardson ,  William Burroughs ,  Joseph Hasting ,  An Yan ,  James Clee ,  Te Ma ,  Jerry Pirog ,  Jamison Whitesell

IPC分类号： G06F13/36 ,  G06F13/40 ,  G06F12/10 ,  G06F13/24

CPC分类号： G06F13/36 ,  G06F12/1027 ,  G06F13/24 ,  G06F13/4004 ,  G06F2212/1021 ,  G06F2212/50 ,  G06F2212/68

摘要： Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

公开(公告)号：US08949838B2

公开(公告)日：2015-02-03

申请号：US13474114

申请日：2012-05-17

申请人： Deepak Mital ,  William Burroughs ,  Eran Dosh ,  Eyal Rosin

发明人： Deepak Mital ,  William Burroughs ,  Eran Dosh ,  Eyal Rosin

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  H04L12/933 ,  H04L12/931 ,  H04L12/851

CPC分类号： G06F9/4881 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/3877 ,  H04L47/2408 ,  H04L47/2441 ,  H04L49/109 ,  H04L49/506

摘要： Described embodiments process multiple threads of commands in a network processor. One or more tasks are generated corresponding to each received packet, and the tasks are provided to a packet processor module (MPP). A scheduler associates each received task with a command flow. A thread updater writes state data corresponding to the flow to a context memory. The scheduler determines an order of processing of the command flows. When a processing thread of a multi-thread processor is available, the thread updater loads, from the context memory, state data for at least one scheduled flow to one of the multi-thread processors. The multi-thread processor processes a next command of the flow based on the loaded state data. If the processed command requires operation of a co-processor module, the multi-thread processor sends a co-processor request and switches command processing from the first flow to a second flow.

摘要翻译： 描述的实施例处理网络处理器中的多个命令线程。 对应于每个接收到的分组生成一个或多个任务，并且将任务提供给分组处理器模块（MPP）。 调度器将每个接收到的任务与命令流相关联。 线程更新器将对应于流的状态数据写入上下文存储器。 调度器确定命令流的处理顺序。 当多线程处理器的处理线程可用时，线程更新器从上下文存储器加载至少一个调度流的状态数据到多线程处理器之一。 多线程处理器基于加载的状态数据处理流的下一个命令。 如果处理的命令需要协处理器模块的操作，则多线程处理器发送协处理器请求并将命令处理从第一流切换到第二流。

公开(公告)号：US08677075B2

公开(公告)日：2014-03-18

申请号：US13359690

申请日：2012-01-27

申请人： Deepak Mital ,  William Burroughs ,  David Sonnier ,  Steven Pollock ,  David Brown ,  Joseph Hasting

发明人： Deepak Mital ,  William Burroughs ,  David Sonnier ,  Steven Pollock ,  David Brown ,  Joseph Hasting

IPC分类号： G06F12/00

CPC分类号： G06F12/123 ,  G06F12/084 ,  H04L49/101 ,  H04L49/109 ,  H04L49/506

摘要： Described embodiments provide a network processor having a plurality of processing modules coupled to a system cache and a shared memory. A memory manager allocates blocks of the shared memory to a requesting one of the processing modules. The allocated blocks store data corresponding to packets received by the network processor. The memory manager maintains a reference count for each allocated memory block indicating a number of processing modules accessing the block. One of the processing modules reads the data stored in the allocated memory blocks, stores the read data to corresponding entries of the system cache and operates on the data stored in the system cache. Upon completion of operation on the data, the processing module requests to decrement the reference count of each memory block. Based on the reference count, the memory manager invalidates the entries of the system cache and deallocates the memory blocks.

摘要翻译： 所描述的实施例提供具有耦合到系统高速缓存和共享存储器的多个处理模块的网络处理器。 存储器管理器将共享存储器的块分配给请求的一个处理模块。 所分配的块存储对应于由网络处理器接收的分组的数据。 存储器管理器为每个分配的存储块维护指示接入该块的处理模块的数量的引用计数。 其中一个处理模块读取存储在分配的存储器块中的数据，将读取的数据存储到系统高速缓存的相应条目，并对存储在系统高速缓存中的数据进行操作。 在完成对数据的操作时，处理模块请求递减每个存储器块的引用计数。 基于引用计数，内存管理器使系统缓存的条目无效，并释放内存块。

公开(公告)号：US08537832B2

公开(公告)日：2013-09-17

申请号：US13046726

申请日：2011-03-12

申请人： Jerry Pirog ,  Deepak Mital ,  William Burroughs

发明人： Jerry Pirog ,  Deepak Mital ,  William Burroughs

IPC分类号： H04L12/28

CPC分类号： G06F15/167 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885

摘要： Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A function bus interface inspects instructions received from the multi-thread instruction engine for one or more exception conditions. If the function bus interface detects an exception, the function bus interface reports the exception to the scheduler and the multi-thread instruction engine. The scheduler reschedules the thread corresponding to the instruction having the exception for processing in the multi-thread instruction engine. Otherwise, the function bus interface provides the instruction to a corresponding destination processing module of the network processor.

摘要翻译： 描述的实施例提供具有多个处理模块的网络处理器的分组分类器。 调度器针对与每个接收的分组相对应的由网络处理器生成的每个任务生成上下文的线程。 线程对应于应用于相应分组的指令的顺序。 多线程指令引擎处理指令的线程。 功能总线接口检查从多线程指令引擎接收的指令是否存在一个或多个异常情况。 如果功能总线接口检测到异常，则功能总线接口向调度程序和多线程指令引擎报告异常。 调度器对与具有用于在多线程指令引擎中进行处理的异常的指令相对应的线程进行重新调度。 否则，功能总线接口向网络处理器的相应目标处理模块提供指令。

公开(公告)号：US08321385B2

公开(公告)日：2012-11-27

申请号：US13046719

申请日：2011-03-12

申请人： William Burroughs ,  Deepak Mital ,  Mohammed Reza Hakami

发明人： William Burroughs ,  Deepak Mital ,  Mohammed Reza Hakami

IPC分类号： G06F7/00 ,  G06F17/00 ,  G06F17/30

CPC分类号： G06F15/167 ,  G06F9/3851 ,  G06F9/3885 ,  H04L45/7453

摘要： Described embodiments provide coherent processing of hash operations of a network processor having a plurality of processing modules. A hash processor of the network processor receives hash operation requests from the plurality of processing modules. A hash table identifier and bucket index corresponding to the received hash operation request are determined. An active index list is maintained for active hash operations for each hash table identifier and bucket index. If the hash table identifier and bucket index of the received hash operation request are in the active index list, the received hash operation request is deferred until the hash table identifier and bucket index corresponding to the received hash operation request clear from the active index list. Otherwise, the active index list is updated with the hash table identifier and bucket index of the received hash operation request and the received hash operation request is processed.

摘要翻译： 所描述的实施例提供具有多个处理模块的网络处理器的散列操作的相干处理。 网络处理器的散列处理器从多个处理模块接收散列操作请求。 确定与所接收的散列操作请求对应的哈希表标识符和桶索引。 为每个哈希表标识符和桶索引的活动散列操作维护活动索引列表。 如果接收到的散列操作请求的散列表标识符和桶索引在活动索引列表中，则接收到的散列操作请求被延迟，直到与所接收的散列操作请求对应的散列表标识符和存储桶索引从活动索引列表中清除。 否则，主动索引列表用哈希表标识符和接收到的散列操作请求的桶索引进行更新，并且处理接收的散列操作请求。