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Patent Agency Ranking
公开(公告)号：US20170011827A1
公开(公告)日：2017-01-12
申请号：US15113397
申请日：2015-01-02
Applicant: EPCOS AG
Inventor： Yasuharu Miyauchi , Pavol Dudesek , Christian Faistauer , Gerhard Fuchs , Stefan Obermair , Klaus-Dieter Aichholzer , Christian Block , Sebastian Brunner
CPC classification number: H01C7/12 , C03C3/089 , H01C7/1006 , H01C7/112 , H01C7/18 , H01C17/285 , H01L25/167 , H01L2924/0002 , H01L2924/00
Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.
Abstract translation: 公开了一种芯片和芯片的制造方法。 在一个实施例中，芯片包括由氧化锌组成的可变电阻层，在压敏电阻层中实现变阻器功能的多层电极结构以及可变阻抗层的第一主表面上的至少两个可焊接或可接合的外部触点。 芯片还包括设置在第一主表面上的玻璃层，仅留下未覆盖的外部触点，其中玻璃层主要包括Si和/或Ge，B和K的氧化物，其总共具有至少70％ 的玻璃层的成分，并且其中玻璃层基本上不含Al，Ga，Cr和Ti。
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公开(公告)号：US10361018B2
公开(公告)日：2019-07-23
申请号：US14407919
申请日：2013-06-06
Applicant: EPCOS AG
Inventor： Franz Rinner , Dieter Somitsch , Christoph Auer , Gerhard Fuchs
IPC: H01C7/00 , H01G4/30 , H01C1/14 , H01C7/18 , H01C17/00 , H01C17/28 , H01G4/012 , H01L41/083 , H01L41/297 , C25F3/00 , H01C7/10 , H01G4/005 , H01L41/047
Abstract: A method for producing a multilayer component (21) is specified, which involves providing a body having dielectric layers (3) arranged one above another and first and second electrically conductive layers (4, 84, 5, 85) arranged therebetween. The first conductive layers (4, 84) are connected to a first auxiliary electrode (6) and the second conductive layers (5, 85) are connected to a second auxiliary electrode (7). The body (1, 81) is introduced into a medium and a voltage is applied between the first and second auxiliary electrodes (6, 7) for producing a material removal. Furthermore, a multilayer component is specified, which has depressions (20) formed by an electrochemically controlled material removal.
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3.发明申请公开(公告)号：US20150123516A1
公开(公告)日：2015-05-07
申请号：US14407919
申请日：2013-06-06
Applicant: EPCOS AG
Inventor： Franz Rinner , Dieter Somitsch , Christoph Auer , Gerhard Fuchs
CPC classification number: H01C7/008 , C25F3/00 , H01C1/14 , H01C7/10 , H01C7/18 , H01C17/006 , H01C17/28 , H01G4/005 , H01G4/012 , H01G4/30 , H01L41/0471 , H01L41/0838 , H01L41/297
Abstract: A method for producing a multilayer component (21) is specified, which involves providing a body having dielectric layers (3) arranged one above another and first and second electrically conductive layers (4, 84, 5, 85) arranged therebetween. The first conductive layers (4, 84) are connected to a first auxiliary electrode (6) and the second conductive layers (5, 85) are connected to a second auxiliary electrode (7). The body (1, 81) is introduced into a medium and a voltage is applied between the first and second auxiliary electrodes (6, 7) for producing a material removal. Furthermore, a multilayer component is specified, which has depressions (20) formed by an electrochemically controlled material removal.
Abstract translation: 具体地说，提供一种制造多层部件（21）的方法，其特征在于，具备设置在彼此上下配置的电介质层（3）的主体以及配置在其间的第一和第二导电层（4,84,55）。 第一导电层（4,84）连接到第一辅助电极（6），第二导电层（5,85）连接到第二辅助电极（7）。 将主体（1,81）引入介质中，并且在第一和第二辅助电极（6,7）之间施加电压以产生材料去除。 此外，指定了具有通过电化学控制的材料去除形成的凹陷（20）的多层部件。
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公开(公告)号：US09865381B2
公开(公告)日：2018-01-09
申请号：US15113397
申请日：2015-01-02
Applicant: EPCOS AG
Inventor： Yasuharu Miyauchi , Pavol Dudesek , Christian Faistauer , Gerhard Fuchs , Stefan Obermair , Klaus-Dieter Aichholzer , Christian Block , Sebastian Brunner
CPC classification number: H01C7/12 , C03C3/089 , H01C7/1006 , H01C7/112 , H01C7/18 , H01C17/285 , H01L25/167 , H01L2924/0002 , H01L2924/00
Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.
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公开(公告)号：US20170311455A1
公开(公告)日：2017-10-26
申请号：US15315359
申请日：2015-08-12
Applicant: EPCOS AG
Inventor： Sebastian Brunner , Gerhard Fuchs , Annette Fischer
CPC classification number: H05K3/429 , H05K1/0306 , H05K1/09 , H05K1/115 , H05K3/248 , H05K3/4061 , H05K3/4605 , H05K2201/0195
Abstract: A method for producing a multilayer substrate (1) is specified, wherein a main body (26) comprising a plurality of ceramic layers (2) is provided, wherein at least one layer (2) comprises a hole (27). In order to form a plated-through hole (4, 18, 20, 21), the hole (27) is filled with a metal by depositing the metal from a solution. Furthermore, a multilayer substrate is specified wherein a plated-through hole (4, 18, 20, 21) in the interior of the main body (26) is connected to a further contact (11), wherein the plated-through hole (4, 18, 20, 21) comprises a different material than the further contact (11) and/or is produced by a different method.macros hash =multilayer substrate star =plated-throuch hole pie =connection contact alpha =photoresist mask beta =further contact gamma =HTCC technology delta =main body matt =ceramic layer
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