公开(公告)号：US09191123B2

公开(公告)日：2015-11-17

申请号：US14642651

申请日：2015-03-09

Applicant: FINISAR CORPORATION

Inventor： Georgios Kalogerakis ,  Lionel Li ,  The'Linh Nguyen

IPC: H04B10/69 ,  H04B10/61

CPC classification number: H04B10/616 ,  H04B10/6971

Abstract: A circuit may include a photodiode configured to receive an optical signal and convert the optical signal to a current signal. The circuit may also include a transimpedance amplifier coupled to the photodiode and configured to convert the current signal to a voltage signal. The circuit may also include an equalizer coupled to the transimpedance amplifier and configured to equalize the voltage signal to at least partially compensate for a loss of a high frequency component of the optical signal. The equalizer and the transimpedance amplifier may be housed within a single integrated circuit.

Abstract translation: 电路可以包括被配置为接收光信号并将光信号转换成电流信号的光电二极管。 电路还可以包括耦合到光电二极管并被配置为将电流信号转换成电压信号的跨阻放大器。 电路还可以包括耦合到跨阻放大器的均衡器，并且被配置为使电压信号均衡以至少部分地补偿光信号的高频分量的损耗。 均衡器和跨阻放大器可以容纳在单个集成电路内。

公开(公告)号：US09146367B2

公开(公告)日：2015-09-29

申请号：US13706454

申请日：2012-12-06

Applicant: Finisar Corporation

Inventor： Georgios Kalogerakis ,  The'Linh Nguyen ,  Jason Miao

IPC: G02B6/42 ,  G02B6/43 ,  H04B10/50

CPC classification number: G02B6/4246 ,  G02B6/4249 ,  G02B6/428 ,  G02B6/43 ,  H04B10/50 ,  Y10T29/49002

Abstract: A modular device for an optical communication module configured to be coupled to an optical transmission medium. The modular device may include a first edge and a second edge and N number of electrical circuit channels between the first and second edges. Each electrical circuit channel may include at least one element configured to provide functionality for communicating optical signals through the optical transmission medium. The modular device may also have a width between the first and second edges so that each of the N number of electrical circuit channels of C number of modular devices aligns with one of P number of interface channels of an opto-electrical interface configured to be coupled to the optical transmission medium when C equals P/N and C is a whole number greater than zero.

Abstract translation: 一种用于光通信模块的模块化设备，其被配置为耦合到光传输介质。 模块化装置可以包括在第一和第二边缘之间的第一边缘和第二边缘以及N个电路通道。 每个电路通道可以包括配置成提供通过光传输介质传送光信号的功能的至少一个元件。 模块化设备还可以具有第一和第二边缘之间的宽度，使得C个模块化设备的N个电路通道中的每一个与光电接口的P个接口通道中的一个对准，该光电接口的接口通道被配置为被耦合 当C等于P / N并且C是大于零的整数时，到光传输介质。

公开(公告)号：US20150180587A1

公开(公告)日：2015-06-25

申请号：US14642651

申请日：2015-03-09

Applicant: FINISAR CORPORATION

Inventor： Georgios Kalogerakis ,  Lionel Li ,  The'Linh Nguyen

IPC: H04B10/61

CPC classification number: H04B10/616 ,  H04B10/6971

Abstract: A circuit may include a photodiode configured to receive an optical signal and convert the optical signal to a current signal. The circuit may also include a transimpedance amplifier coupled to the photodiode and configured to convert the current signal to a voltage signal. The circuit may also include an equalizer coupled to the transimpedance amplifier and configured to equalize the voltage signal to at least partially compensate for a loss of a high frequency component of the optical signal. The equalizer and the transimpedance amplifier may be housed within a single integrated circuit.

Abstract translation: 电路可以包括被配置为接收光信号并将光信号转换成电流信号的光电二极管。 电路还可以包括耦合到光电二极管并被配置为将电流信号转换成电压信号的跨阻放大器。 电路还可以包括耦合到跨阻放大器的均衡器，并且被配置为使电压信号均衡以至少部分地补偿光信号的高频分量的损耗。 均衡器和跨阻放大器可以容纳在单个集成电路内。

公开(公告)号：US09014322B2

公开(公告)日：2015-04-21

申请号：US13757665

申请日：2013-02-01

Applicant: Finisar Corporation

Inventor： The'Linh Nguyen ,  Steven Gregory Troyer ,  Daniel K. Case

IPC: H03D3/24 ,  H04L7/00 ,  H04L7/033 ,  H03L7/093

CPC classification number: H03L7/091 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/093 ,  H04L7/0016 ,  H04L7/033

Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.

Abstract translation: 在示例性实施例中，锁相环电路可以包括用于接收参考信号和源信号的第一电路。 第一电路可以产生用于示出参考信号和源信号之间的相位差的校正信号。 锁相环可以包括用于接收校正信号的第二电路。 第二电路可以产生用于演示校正信号的相位到数字转换的数字信号。 锁相环可以包括用于接收数字信号的第三电路。 第三电路可以产生用于演示数字信号的转换电压的控制信号。 锁相环可以包括用于接收控制信号的第四电路。 第四电路可以响应于控制信号产生源信号。

公开(公告)号：US09866330B2

公开(公告)日：2018-01-09

申请号：US14612035

申请日：2015-02-02

Applicant: FINISAR CORPORATION

Inventor： The'Linh Nguyen ,  Henry M. Daghighian

IPC: H04B10/50 ,  H04B10/564 ,  H04B10/25 ,  H04L25/03 ,  H04B10/2575

CPC classification number: H04B10/564 ,  H04B10/2504 ,  H04B10/2575 ,  H04L25/03847

Abstract: In one example embodiment, a transmitter module includes a header electrically coupled to a chassis ground. First and second input nodes are configured to receive a differential data signal. A buffer stage has a first node coupled to the first input node and a second node coupled to the second input node. An amplifier stage has a fifth node coupled to a third node of the buffer stage and a sixth node coupled to a signal ground that is not coupled to the chassis ground. An optical transmitter has an eighth node coupled to a seventh node of the amplifier stage and a ninth node configured to be coupled to a voltage source. A bias circuit is configured to couple a fourth node of the buffer stage to a bias current source.

公开(公告)号：US09306546B2

公开(公告)日：2016-04-05

申请号：US13761036

申请日：2013-02-06

Applicant: FINISAR CORPORATION

Inventor： Henry M. Daghighian ,  Luke M Ekkizogloy ,  The'Linh Nguyen ,  Christopher Kocot ,  James Prettyleaf

IPC: H03K17/00 ,  H03K3/013 ,  H03K7/08 ,  H04B10/40

CPC classification number: H03K3/013 ,  H03K7/08 ,  H03K19/21 ,  H04B10/40

Abstract: An example embodiment includes a fiber optic integrated circuit (IC). The fiber optic IC includes an integrated power supply. The integrated power supply includes a filter, an active switch, and a pulse width modulator (“PWM”). The filter is configured to convert a signal to an output signal of the integrated power supply. The active switch is configured to control introduction of the signal to the filter. The PWM is configured to generate a PWM output signal that triggers the active switch.

Abstract translation: 示例实施例包括光纤集成电路（IC）。 光纤IC包括集成电源。 集成电源包括滤波器，有源开关和脉宽调制器（“PWM”）。 滤波器被配置为将信号转换成集成电源的输出信号。 有源开关被配置为控制信号到滤波器的引入。 PWM被配置为产生触发有源开关的PWM输出信号。

公开(公告)号：US09172473B2

公开(公告)日：2015-10-27

申请号：US13916406

申请日：2013-06-12

Applicant: FINISAR CORPORATION

Inventor： The'Linh Nguyen ,  Henry M. Daghighian

IPC: H04B10/58 ,  H04B10/564 ,  H04B10/25 ,  H04L25/03 ,  H04B10/2575

CPC classification number: H04B10/564 ,  H04B10/2504 ,  H04B10/2575 ,  H04L25/03847

Abstract: In one example embodiment, a transmitter module includes a header electrically coupled to a chassis ground. First and second input nodes are configured to receive a differential data signal. A buffer stage has a first node coupled to the first input node and a second node coupled to the second input node. An amplifier stage has a fifth node coupled to a third node of the buffer stage and a sixth node coupled to a signal ground that is not coupled to the chassis ground. An optical transmitter has an eighth node coupled to a seventh node of the amplifier stage and a ninth node configured to be coupled to a voltage source. A bias circuit is configured to couple a fourth node of the buffer stage to a bias current source.

Abstract translation: 在一个示例实施例中，发射机模块包括电耦合到底盘接地的接头。 第一和第二输入节点被配置为接收差分数据信号。 缓冲器级具有耦合到第一输入节点的第一节点和耦合到第二输入节点的第二节点。 放大器级具有耦合到缓冲级的第三节点的第五节点和耦合到未耦合到机架接地的信号地的第六节点。 光发射机具有耦合到放大器级的第七节点的第八节点和被配置为耦合到电压源的第九节点。 偏置电路被配置为将缓冲器级的第四节点耦合到偏置电流源。

公开(公告)号：US09705503B2

公开(公告)日：2017-07-11

申请号：US15194416

申请日：2016-06-27

Applicant: FINISAR CORPORATION

Inventor： The'Linh Nguyen

IPC: H03K19/094 ,  H03K19/185 ,  H03K19/0185 ,  H03K19/018 ,  H03K3/017 ,  H03K19/0175 ,  H03K5/156

CPC classification number: H03K19/018528 ,  H03K3/017 ,  H03K5/1565 ,  H03K19/017509 ,  H03K19/01806 ,  H03K19/018514

Abstract: A circuit may include an input terminal configured to receive an input signal with a first voltage swing and an output terminal. The circuit may also include a first transistor, a second transistor, a third transistor, and a control circuit. The control circuit may be coupled to the input terminal, a gate terminal of the first transistor, and a gate terminal of the second transistor. The control circuit may be configured to adjust voltages provided to the gate terminals based on the input signal such that the first transistor conducts in response to the input signal being at a first logical level and the second transistor conducts in response to the input signal being at a second logical level to generate an output signal output on the output terminal. The second voltage swing of the output signal may be different from the first voltage swing of the input signal.

公开(公告)号：US20160013800A1

公开(公告)日：2016-01-14

申请号：US14691558

申请日：2015-04-20

Applicant: FINISAR CORPORATION

Inventor： The'Linh Nguyen ,  Steven Gregory Troyer ,  Daniel K. Case

IPC: H03L7/091 ,  H04L7/00

CPC classification number: H03L7/091 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/093 ,  H04L7/0016 ,  H04L7/033

Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.

公开(公告)号：US20130315349A1

公开(公告)日：2013-11-28

申请号：US13757665

申请日：2013-02-01

Applicant: FINISAR CORPORATION

Inventor： The'Linh Nguyen ,  Steven Gregory Troyer ,  Daniel K. Case

IPC: H04L7/00

CPC classification number: H03L7/091 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/093 ,  H04L7/0016 ,  H04L7/033

Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.

Abstract translation: 在示例性实施例中，锁相环电路可以包括用于接收参考信号和源信号的第一电路。 第一电路可以产生用于示出参考信号和源信号之间的相位差的校正信号。 锁相环可以包括用于接收校正信号的第二电路。 第二电路可以产生用于演示校正信号的相位到数字转换的数字信号。 锁相环可以包括用于接收数字信号的第三电路。 第三电路可以产生用于演示数字信号的转换电压的控制信号。 锁相环可以包括用于接收控制信号的第四电路。 第四电路可以响应于控制信号产生源信号。