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    Low loss interconnect structure for use in microelectronic circuits
    1.
    发明申请
    Low loss interconnect structure for use in microelectronic circuits 有权
    用于微电子电路的低损耗互连结构

    公开(公告)号：US20050227507A1

    公开(公告)日：2005-10-13

    申请号：US11152643

    申请日：2005-06-14

    申请人： Frank O'Mahony ,  Mark Anders ,  Krishnamurthy Soumyanath

    发明人： Frank O'Mahony ,  Mark Anders ,  Krishnamurthy Soumyanath

    IPC分类号： H01L23/522 ,  H01R12/00

    CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

    摘要翻译： 低损耗管芯互连结构包括在微电子管芯的金属层之一上的第一和第二差分信号线。 还可以在与差分信号线不平行（例如，正交））的管芯的另一金属层上提供一个或多个迹线。 由于迹线不平行，它们为差分信号线上的信号提供了相对较高的阻抗返回路径。 因此，通过相反的微分线路的信号返回路径对于差分线路上的信号占优势。 在一个应用中，低损耗互连结构用于管芯内的相关时钟分配网络。

    Low loss interconnect structure for use in microelectronic circuits
    3.
    发明授权
    Low loss interconnect structure for use in microelectronic circuits 有权
    用于微电子电路的低损耗互连结构

    公开(公告)号：US07352059B2

    公开(公告)日：2008-04-01

    申请号：US11152643

    申请日：2005-06-14

    申请人： Frank O'Mahony ,  Mark A. Anders ,  Krishnamurthy Soumyanath

    发明人： Frank O'Mahony ,  Mark A. Anders ,  Krishnamurthy Soumyanath

    IPC分类号： H01L27/10 ,  H01L23/52 ,  H01L23/522 ,  H01R12/00

    CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

    摘要翻译： 低损耗管芯互连结构包括在微电子管芯的金属层之一上的第一和第二差分信号线。 还可以在与差分信号线不平行（例如，正交））的管芯的另一金属层上提供一个或多个迹线。 由于迹线不平行，它们为差分信号线上的信号提供了相对较高的阻抗返回路径。 因此，通过相反的微分线路的信号返回路径对于差分线路上的信号占优势。 在一个应用中，低损耗互连结构用于管芯内的相关时钟分配网络。

    Hierarchical clock grid for on-die salphasic clocking
    4.
    发明授权
    Hierarchical clock grid for on-die salphasic clocking 失效
    分层时钟网格，用于芯片上的相关时钟

    公开(公告)号：US06522186B2

    公开(公告)日：2003-02-18

    申请号：US09893067

    申请日：2001-06-27

    申请人： Frank O'Mahony ,  Mark A. Anders ,  Krishnamurthy Soumyanath

    发明人： Frank O'Mahony ,  Mark A. Anders ,  Krishnamurthy Soumyanath

    IPC分类号： G06F104

    CPC分类号： G06F1/10

    摘要： A hierarchical clock distribution system includes a global clock grid that distributes a clock signal to a plurality of regional clock grids. Each of the regional clock grids then distributes the signal to a plurality of corresponding loads. The regional clock grids utilize salphasic clocking techniques to distribute the clock signal to the corresponding loads. The global grid achieves low skew based on the periodicity of the clock signal, rather than the dominance of a standing wave. The electrical distance to termination within the regional clock grids is preferably kept low to avoid the occurrence of phase change regions on the regional grids. In one approach, the regional grids are each driven at multiple points in a symmetrical fashion to reduce the electrical distance to termination.

    摘要翻译： 分层时钟分配系统包括将时钟信号分配到多个区域时钟网格的全局时钟网格。 然后，每个区域时钟网格将信号分配给多个对应的负载。 区域时钟网格利用相关的时钟技术将时钟信号分配给相应的负载。 基于时钟信号的周期性，全球电网实现了低偏移，而不是驻波的优势。 区域时钟网格内的终端电气距离优选保持较低，以避免在区域网格上发生相变区域。 在一种方法中，区域网格以对称方式被驱动在多个点，以减少到终止的电距离。

    Integrated circuit passive signal distribution
    6.
    发明授权
    Integrated circuit passive signal distribution 有权
    集成电路无源信号分配

    公开(公告)号：US08571513B2

    公开(公告)日：2013-10-29

    申请号：US13540500

    申请日：2012-07-02

    申请人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

    发明人： Frank O'Mahony ,  Bryan Casper ,  James Jaussi ,  Matthew B. Haycock ,  Joseph Kennedy ,  Mozhgan Mansuri ,  Stephen R. Mooney

    IPC分类号： H04B1/28

    CPC分类号： H04L25/0278 ,  H03K5/15013 ,  H04L25/0292 ,  H04L25/0298

    摘要： For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，集成电路可以包括集成电路的一个或多个层中的内部传输线。 内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号，而不使用终端电路。 内部传输线路可以将信号被动地发送到内部传输线路的第二端。 集成电路还可以包括第一电路，其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号，并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入 线接收信号。 第二位置可以不同于第一位置。 还公开了其他实施例。

    MACRO-TRANSISTOR DEVICES
    8.
    发明申请
    MACRO-TRANSISTOR DEVICES 有权
    宏器件设备

    公开(公告)号：US20140008732A1

    公开(公告)日：2014-01-09

    申请号：US13976081

    申请日：2011-11-14

    申请人： Sami Hyvonen ,  Jad B. Rizk ,  Frank O'Mahony

    发明人： Sami Hyvonen ,  Jad B. Rizk ,  Frank O'Mahony

    IPC分类号： H01L27/088

    CPC分类号： H01L27/0886 ,  H01L27/088 ,  H01L27/1211 ,  H01L29/42376 ,  H01L29/66181 ,  H01L29/785 ,  H01L29/93 ,  H01L29/94 ,  H03L7/099

    摘要： Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to long-channel transistors, but are suitable for analog circuits in deep submicron technologies deep-submicron process nodes. The macro-transistor structures can be implemented, for instance, with a plurality of transistors constructed and arranged in series, and with their gates tied together, generally referred to herein as a transistor stack. One or more of the serial transistors within the stack can be implemented with a plurality of parallel transistors and/or can have a threshold voltage different that is different from the threshold voltages of other transistors in the stack. Alternatively, or in addition, one or more of the serial transistors within the macro-transistor can be statically or dynamically controlled to tune the performance characteristics of the macro-transistor. The macro-transistors can be used in numerous circuits, such as varactors, VCOs, PLLs, and tunable circuits.

    摘要翻译： 公开了宏观晶体管结构。 在一些情况下，宏晶体管结构具有与长沟道晶体管类似的端子和性质相同的数量，但适用于深亚微米技术深亚微米工艺节点中的模拟电路。 宏晶体管结构可以例如通过串联构造和布置的多个晶体管实现，并且其栅极连接在一起，这里通常称为晶体管堆叠。 堆叠内的一个或多个串联晶体管可以用多个并联晶体管实现和/或可以具有不同于堆叠中其它晶体管的阈值电压的阈值电压。 或者或另外，宏晶体管内的一个或多个串联晶体管可以被静态或动态地控制，以调整宏晶体管的性能特性。 宏晶体管可用于许多电路，例如变容二极管，VCO，PLL和可调谐电路。

    Time-domain device noise simulator
    10.
    发明申请
    Time-domain device noise simulator 失效
    时域设备噪声模拟器

    公开(公告)号：US20070233444A1

    公开(公告)日：2007-10-04

    申请号：US11395537

    申请日：2006-03-31

    申请人： Frank O'Mahony ,  Haydar Kutuk ,  Bryan Casper ,  Eyal Fayneh ,  Sivakumar Mudanai ,  Wei-kai Shih ,  Farag Fattouh

    发明人： Frank O'Mahony ,  Haydar Kutuk ,  Bryan Casper ,  Eyal Fayneh ,  Sivakumar Mudanai ,  Wei-kai Shih ,  Farag Fattouh

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.

    摘要翻译： 通常，在一个方面，本公开描述了一种用于在时域电路仿真中模拟各种类型的器件噪声的模拟器。 模拟器能够为晶体管以及无源元件（如电阻）增加噪声。 模拟器使用与设备并联的至少一个电流源来模拟噪声。 电流源产生随机电流输出以根据随机高斯数和器件噪声的标准偏差来模拟器件噪声。 可以基于在该模拟时间和更新时间具有特定偏压的装置的噪声功率谱密度来确定噪声标准偏差。 模拟器能够通过利用具有不同更新步骤的多个电流源来模拟具有恒定或单调降低的噪声频谱（例如，热噪声，闪烁噪声）的任何噪声源。 模拟器与标准电路模拟器兼容。