公开(公告)号：US09947791B2

公开(公告)日：2018-04-17

申请号：US13965322

申请日：2013-08-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Chun-chen Yeh ,  Yunpeg Yin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

公开(公告)号：US10529858B2

公开(公告)日：2020-01-07

申请号：US15913194

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

公开(公告)号：US09646929B2

公开(公告)日：2017-05-09

申请号：US13916669

申请日：2013-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hsueh-Chung Chen ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Ailian Zhao

IPC: H01L23/525 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L21/76888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask.

公开(公告)号：US09293345B2

公开(公告)日：2016-03-22

申请号：US13968807

申请日：2013-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/302 ,  H01L21/311 ,  H01L29/78 ,  H01L21/308 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/31111 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and sidewall image transfer methods with a spin on hardmask. Methods for forming fins include forming a trench through a stack of layers that includes a top and bottom insulator layer, and a layer to be patterned on a substrate; isotropically etching the top and bottom insulator layers; forming a hardmask material in the trench to the level of the bottom insulator layer; isotropically etching the top insulator layer; and etching the bottom insulator layer and the layer to be patterned down to the substrate to form fins from the layer to be patterned.

Abstract translation: 半导体器件和侧壁图像传输方法，在硬掩模上旋转。 用于形成翅片的方法包括通过包括顶部和底部绝缘体层的层叠层和在基底上待图案化的层形成沟槽; 各向同性蚀刻顶部和底部绝缘体层; 在所述沟槽中形成硬掩模材料至所述底部绝缘体层的水平面; 各向同性蚀刻顶部绝缘体层; 并且将底部绝缘体层和待图案化的层蚀刻到衬底上以从待图案化的层形成翅片。

公开(公告)号：US20140367826A1

公开(公告)日：2014-12-18

申请号：US13916669

申请日：2013-06-13

Applicant: GLOBALFOUNDRIES, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Ailian Zhao

IPC: H01L21/768 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/76888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask.

Abstract translation: 公开了晶片芯片和芯片的设计方法。 形成具有第一临界尺寸的第一熔丝，并且在芯片的层中形成具有第二临界尺寸的第二熔丝。 可以施加电压以烧尽第一保险丝和第二保险丝中的至少一个。 第一保险丝的第一关键尺寸可以是将第一掩模施加到该层并且将具有第一特性的光施加到掩模。 第二保险丝的第二关键尺寸可以是将第二掩模应用于该层并且将具有第二特性的光施加到掩模。

公开(公告)号：US20140273443A1

公开(公告)日：2014-09-18

申请号：US13834946

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC. ,  RENESAS ELECTRONICS CORPORATION ,  INTERNATIONL BUSINESS MACHINES CORPORATION

Inventor： Linus Jang ,  Yoshinori Matsui ,  Chiahsun Tseng

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144

Abstract: One illustrative method disclosed herein involves forming a layer of insulating material, forming a patterned layer of photoresist above the layer of insulating material, wherein the patterned layer of photoresist has an opening defined therein, forming an internal spacer within the opening in the patterned layer of photoresist, wherein the spacer defines a reduced-size opening, performing an etching process through the reduced-size opening on the layer of insulating material to define a trench/hole type feature in the layer of insulating material, and forming a conductive structure in the trench/hole type feature in the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括形成绝缘材料层，在绝缘材料层之上形成图案化的光致抗蚀剂层，其中所述图案化的光致抗蚀剂层具有限定在其中的开口，在图案化层中的开口内形成内部间隔物 光致抗蚀剂，其中间隔物限定尺寸较小的开口，通过绝缘材料层上的尺寸减小的开口执行蚀刻工艺，以在绝缘材料层中限定沟槽/孔型特征，并在该层中形成导电结构 绝缘材料层中的沟槽/孔型特征。

公开(公告)号：US20180197980A1

公开(公告)日：2018-07-12

申请号：US15913194

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.