公开(公告)号：US10170304B1

公开(公告)日：2019-01-01

申请号：US15793621

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Oh-Jung Kwon ,  Claude Ortolland ,  Dominic Schepis ,  Christopher Collins

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned nanotube structures and methods of manufacture. The structure includes at least one nanotube structure supported by a plurality of spacers and an insulator material between the spacers and contacting the at least one nanotube structure.

公开(公告)号：US20170345719A1

公开(公告)日：2017-11-30

申请号：US15163313

申请日：2016-05-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bhupesh Chandra ,  Claude Ortolland ,  Gregory G. Freeman ,  Viorel Ontalus ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Paul Chang

IPC: H01L21/8234 ,  H01L21/32 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L21/823418 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/32 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/6656

Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

公开(公告)号：US09620384B2

公开(公告)日：2017-04-11

申请号：US14323036

申请日：2014-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Claude Ortolland ,  Kai Zhao

IPC: H01L21/3115 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L21/3115 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28176 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor structure, by depositing a dielectric layer is a dummy gate, or an existing gate structure, prior to the formation of gate spacers. Following the formation of spacers, and in some embodiments replacing a dummy gate with a final gate structure, oxygen is introduced to a gate dielectric through a diffusion process, using the deposited dielectric layer as a diffusion pathway.

公开(公告)号：US09953873B2

公开(公告)日：2018-04-24

申请号：US15163313

申请日：2016-05-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bhupesh Chandra ,  Claude Ortolland ,  Gregory G. Freeman ,  Viorel Ontalus ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Paul Chang

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/32 ,  H01L27/088

CPC classification number: H01L21/823418 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/32 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/6656

Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

公开(公告)号：US20170256565A1

公开(公告)日：2017-09-07

申请号：US15060067

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Karen A. Nummy ,  Claude Ortolland

IPC: H01L27/12 ,  H01L29/161 ,  H01L29/10 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/7842 ,  H01L29/78684

Abstract: Device structures for a field-effect transistor and methods of forming such device structures using a device layer of a silicon-on-insulator substrate. A channel and an isolation region are formed in the device layer. The channel is located beneath a gate structure is formed on the device layer and is comprised of a semiconductor material under strain. A portion of the device layer is located between the first isolation region and the channel. The portion of the device layer is under a strain that is less than the strain in the semiconductor material of the channel.

公开(公告)号：US09722045B2

公开(公告)日：2017-08-01

申请号：US14921434

申请日：2015-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bhupesh Chandra ,  Viorel Ontalus ,  Timothy J. McArdle ,  Paul Chang ,  Claude Ortolland ,  Judson R. Holt

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/225

CPC classification number: H01L29/66575 ,  H01L21/2254 ,  H01L21/2257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.

公开(公告)号：US09871057B2

公开(公告)日：2018-01-16

申请号：US15060067

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Karen A. Nummy ,  Claude Ortolland

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/06 ,  H01L29/161 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/10

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/7842 ,  H01L29/78684

Abstract: Device structures for a field-effect transistor and methods of forming such device structures using a device layer of a silicon-on-insulator substrate. A channel and an isolation region are formed in the device layer. The channel is located beneath a gate structure is formed on the device layer and is comprised of a semiconductor material under strain. A portion of the device layer is located between the first isolation region and the channel. The portion of the device layer is under a strain that is less than the strain in the semiconductor material of the channel.

公开(公告)号：US20170117387A1

公开(公告)日：2017-04-27

申请号：US14921434

申请日：2015-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bhupesh Chandra ,  Viorel Ontalus ,  Timothy J. McArdle ,  Paul Chang ,  Claude Ortolland ,  Judson R. Holt

IPC: H01L29/66 ,  H01L21/225

CPC classification number: H01L29/66575 ,  H01L21/2254 ,  H01L21/2257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.

公开(公告)号：US09269786B2

公开(公告)日：2016-02-23

申请号：US14037423

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I-Chih Chou ,  Arvind Kumar ,  Shreesh Narasimha ,  Claude Ortolland ,  Kai Zhao

IPC: H01L29/76 ,  H01L29/51 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/518 ,  H01L21/28176 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: Standard High-K metal gate (HKMG) CMOS technologies fabricated using the replacement metal gate (RMG), also known as gate-last, integration flow, are susceptible to oxygen ingress into the high-K gate dielectric layer and oxygen diffusion into the gate dielectric and semiconductor channel region. The oxygen at the gate dielectric and semiconductor channel interface induces unwanted oxide regrowth that results in an effective oxide thickness increase, and transistor threshold voltage shifts, both of which are highly variable and degrade semiconductor chip performance. By introducing silicon nitride deposited at low temperature, after the metal gate formation, the oxygen ingress and gate dielectric regrowth can be avoided, and a high semiconductor chip performance is maintained.

Abstract translation: 使用替代金属栅极（RMG）制造的标准高K金属栅极（HKMG）CMOS技术也被称为最终集成流，易受氧进入高K栅介质层和氧气扩散入栅极 电介质和半导体沟道区。 栅极电介质和半导体沟道界面处的氧会引起不必要的氧化物再生长，导致有效的氧化物厚度增加，并且晶体管阈值电压偏移，这两者都是高度可变的并且降低半导体芯片性能。 通过引入在低温下沉积的氮化硅，在金属栅极形成之后，可以避免氧进入和栅介质再生长，并且保持高的半导体芯片性能。