公开(公告)号：US20160172251A1

公开(公告)日：2016-06-16

申请号：US14567544

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Klaus Hempel ,  Dina Triyoso

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/823828 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: Integrated circuits and methods of forming the same are provided. An exemplary method of forming an integrated circuit includes forming a dummy gate structure overlying a semiconductor substrate. The dummy gate structure includes a gate dielectric layer, a dummy gate layer, an etch stop layer, and a dummy gate cap layer. First sidewall spacers are formed adjacent to sidewalls of the dummy gate structure. A source and drain region are formed in the semiconductor substrate adjacent to the first sidewall spacers. A dielectric material is deposited adjacent to the first sidewall spacers. The dummy gate cap layer is etched with a first etchant selective thereto after depositing the dielectric material. The etch stop layer is etched with a second etchant that is selective thereto. The dummy gate layer is etched to form a gate recess, and a gate material is deposited in the gate recess.

Abstract translation: 提供了集成电路及其形成方法。 形成集成电路的示例性方法包括形成覆盖半导体衬底的虚拟栅极结构。 虚拟栅极结构包括栅极介电层，虚拟栅极层，蚀刻停止层和虚拟栅极覆盖层。 在虚拟栅极结构的侧壁附近形成第一侧壁间隔物。 源极和漏极区域形成在与第一侧壁间隔物相邻的半导体衬底中。 电介质材料沉积在第一侧壁间隔物附近。 在沉积介电材料之后，用选择性的第一蚀刻剂来蚀刻伪栅极盖层。 蚀刻停止层用对其选择的第二蚀刻剂进行蚀刻。 蚀刻虚拟栅极层以形成栅极凹槽，并且栅极材料沉积在栅极凹部中。

公开(公告)号：US20140242788A1

公开(公告)日：2014-08-28

申请号：US13775416

申请日：2013-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gabriela Dilliway ,  Dina Triyoso ,  Elke Erben ,  Rimoon Agaiby

IPC: H01L21/28

CPC classification number: H01L21/28255 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66651

Abstract: One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.

Abstract translation: 本文公开的一种说明性方法包括在小于400℃的温度下进行原子层沉积（ALD）工艺，以在半导体材料的含锗区域上沉积二氧化硅层并形成晶体管器件的栅极结构 在二氧化硅层之上。

公开(公告)号：US09917016B2

公开(公告)日：2018-03-13

申请号：US14567544

申请日：2014-12-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Klaus Hempel ,  Dina Triyoso

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/823828 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656

Abstract: Integrated circuits and methods of forming the same are provided. An exemplary method of forming an integrated circuit includes forming a dummy gate structure overlying a semiconductor substrate. The dummy gate structure includes a gate dielectric layer, a dummy gate layer, an etch stop layer, and a dummy gate cap layer. First sidewall spacers are formed adjacent to sidewalls of the dummy gate structure. A source and drain region are formed in the semiconductor substrate adjacent to the first sidewall spacers. A dielectric material is deposited adjacent to the first sidewall spacers. The dummy gate cap layer is etched with a first etchant selective thereto after depositing the dielectric material. The etch stop layer is etched with a second etchant that is selective thereto. The dummy gate layer is etched to form a gate recess, and a gate material is deposited in the gate recess.

公开(公告)号：US10109492B2

公开(公告)日：2018-10-23

申请号：US13775416

申请日：2013-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gabriela Dilliway ,  Dina Triyoso ,  Elke Erben ,  Rimoon Agaiby

IPC: H01L21/28 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66

Abstract: One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.

公开(公告)号：US09466661B2

公开(公告)日：2016-10-11

申请号：US14511746

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dina Triyoso ,  Shao-Fu Sanford Chu ,  Bo Yu

IPC: H01L49/02 ,  H01L27/08

CPC classification number: H01L28/60 ,  H01L27/0805

Abstract: Methods for fabricating MIM capacitors with low VCC or decoupling and analog/RF capacitors on a single chip and the resulting devices are provided. Embodiments include forming: first and second metal lines in a substrate; a first electrode over, but insulated from, the first metal line; a first high-k dielectric layer on the first electrode, the first high-k dielectric layer having a coefficient α; a second electrode on the first high-k dielectric layer and over a portion of the first electrode; a second high-k dielectric layer on the second electrode, the second high-k dielectric layer having a coefficient α′ opposite in polarity but substantially equal in magnitude to α; a third electrode on the second high-k dielectric layer over the entire first electrode; and a metal-filled via through a dielectric layer down to the first metal line, and a metal-filled via through the dielectric layer down to the second metal line.

Abstract translation: 提供了在单个芯片上制造具有低VCC或去耦的MIM电容器和模拟/ RF电容器的方法以及所得到的器件。 实施例包括在衬底中形成第一和第二金属线; 第一电极，但与第一金属线绝缘; 在第一电极上的第一高k电介质层，第一高k电介质层具有系数α; 在第一高k电介质层上并在第一电极的一部分上的第二电极; 在第二电极上的第二高k电介质层，第二高k电介质层具有极性相反的系数α'，而与α大致相等; 在整个第一电极上的第二高k电介质层上的第三电极; 以及通过电介质层向下延伸到第一金属线的金属填充的通孔，以及通过介电层的金属填充的通孔，直到第二金属线。

公开(公告)号：US20150146341A1

公开(公告)日：2015-05-28

申请号：US14092431

申请日：2013-11-27

Applicant: GLOBALFOUNDRIES, Inc. ,  Intermolecular Inc.

Inventor： Nobumichi Fuchigami ,  David Paul Brunco ,  Karthik Ramani ,  Dina Triyoso

IPC: H01G4/10 ,  C23C16/455 ,  H01G4/30

CPC classification number: H01G4/10 ,  C23C16/403 ,  C23C16/405 ,  C23C16/45525 ,  H01G4/085 ,  H01G4/1281 ,  H01G4/306 ,  H01G4/33 ,  H01L28/40

Abstract: A thin sub-layer ( 12) host material. The sub-layer may be formed by atomic layer deposition (ALD). The layer and sub-layer are annealed to form a composite dielectric layer. The host material crystallizes, but the crystalline lattice and grain boundaries are disrupted near the impurity sub-layer, impeding the migration of electrons. The impurity may be a material with a lower dielectric constant than the high-k material, added in such a small relative amount that the composite dielectric is still high-k. Metal-insulator-metal capacitors may be fabricated by forming the composite dielectric layer between two electrodes.

Abstract translation: 在高k（k> 12）主体材料的较厚层（〜30-100）的下面，上方或内部形成杂质的薄亚层（<15Å）。 子层可以通过原子层沉积（ALD）形成。 层和子层进行退火以形成复合介电层。 主体材料结晶，但晶格和晶界在杂质子层附近被破坏，阻碍了电子迁移。 杂质可以是具有比高k材料低的介电常数的材料，以如此小的相对量添加复合电介质仍然高k。 可以通过在两个电极之间形成复合介电层来制造金属 - 绝缘体 - 金属电容器。

公开(公告)号：US20130270656A1

公开(公告)日：2013-10-17

申请号：US13744601

申请日：2013-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dina Triyoso ,  Hao Zhang

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/32139 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present disclosure is generally directed to various replacement gate structures for semiconductor devices. One illustrative gate structure disclosed herein includes, among other things, a gate insulation layer and a layer of gate electrode material with a substantially horizontal portion having a first thickness and a substantially vertical portion having a second thickness that is less than the first thickness. Furthermore, the substantially horizontal portion of the layer of gate electrode material is positioned adjacent to a bottom of the replacement gate structure and above at least a portion of the gate insulation layer, and the substantially vertical portion is positioned adjacent to sidewalls of the replacement gate structure.

Abstract translation: 本公开一般涉及用于半导体器件的各种替代栅极结构。 本文公开的一种说明性的栅极结构尤其包括栅极绝缘层和栅极电极材料层，其具有基本上水平的部分，具有第一厚度和具有小于第一厚度的第二厚度的基本上垂直的部分。 此外，栅极电极材料层的基本上水平的部分位于邻近替换栅极结构的底部并且位于栅极绝缘层的至少一部分上方，并且基本上垂直的部分邻近置换栅极的侧壁定位 结构体。