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    Devices and methods of forming low resistivity noble metal interconnect
    1.
    发明授权
    Devices and methods of forming low resistivity noble metal interconnect 有权

    公开(公告)号：US10679937B2

    公开(公告)日：2020-06-09

    申请号：US15785665

    申请日：2017-10-17

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528

    Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

    Via and skip via structures
    2.
    发明授权
    Via and skip via structures 有权

    公开(公告)号：US10485111B2

    公开(公告)日：2019-11-19

    申请号：US15647400

    申请日：2017-07-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Shao Beng Law ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  James McMahon ,  Ryan S. Smith ,  Xunyuan Zhang

    IPC: H05K3/46 ,  H05K3/40 ,  H05K1/11 ,  H01L21/768

    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

    Metallization levels and methods of making thereof
    6.
    发明授权
    Metallization levels and methods of making thereof 有权

    公开(公告)号：US10134580B1

    公开(公告)日：2018-11-20

    申请号：US15677693

    申请日：2017-08-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Nicholas V. LiCausi ,  Errol Todd Ryan ,  Sean Xuan Lin

    IPC: H01L21/02 ,  H01L21/48 ,  H01L21/3213 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

    Abstract: Structures for metallization levels of integrated circuits and associated fabrication methods. A first metallization level with a metallization line is formed. A second metallization level is formed over the first metallization level, having two metallization lines and two conductive vias extending from the two metallization lines to the metallization line in the first metallization level. The first metallization line is separated into a first section and a second section disconnected from the first section, so that the first section is connected by one conductive via to one metallization line in the second metallization level, and the second section is connected by the other conductive via to the other metallization line in the second level.

    METHODS OF FORMING AN IMPROVED VIA TO CONTACT INTERFACE BY SELECTIVE FORMATION OF A METAL SILICIDE CAPPING LAYER
    9.
    发明申请
    METHODS OF FORMING AN IMPROVED VIA TO CONTACT INTERFACE BY SELECTIVE FORMATION OF A METAL SILICIDE CAPPING LAYER 有权
    通过选择性形成金属硅化物覆盖层来形成接触界面的方法

    公开(公告)号：US20160126135A1

    公开(公告)日：2016-05-05

    申请号：US14526729

    申请日：2014-10-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Errol Todd Ryan

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

    CPC classification number: H01L21/76883 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact.

    Abstract translation: 本文公开的一种说明性方法包括在至少一层绝缘材料中形成开口，从而暴露至少一部分导电接触，进行选择性金属硅化物形成工艺以选择性地形成金属硅化物层 在所述开口中和在所述导电接触件上，在所述选择性形成的金属硅化物层上方沉积至少一种导电材料，以便过度填充所述开口，并进行至少一个平坦化处理，以便去除多余的材料，从而限定导电通孔 其位于开口中并且导电地耦合到选择性形成的金属硅化物层和导电接触。

    Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device
    10.
    发明授权
    Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device 有权
    形成用于导电铜结构的铜基氮化物衬垫/钝化层的方法以及所得到的器件

    公开(公告)号：US08859419B2

    公开(公告)日：2014-10-14

    申请号：US13757338

    申请日：2013-02-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

    IPC: H01L23/58 ,  H01L29/04 ,  H01L31/036 ,  H01L29/06 ,  H01L31/0352 ,  H01L23/22 ,  H01L23/24 ,  H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

    Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中形成阻挡层，在阻挡层上形成铜基种子层，将至少一部分铜基 种子层形成铜基氮化物层，在铜基氮化物层上沉积大块铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺，以去除位于沟槽之外的多余材料 / via，从而限定铜基导电结构。 本文公开的装置包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和层之间的铜基硅或氮化锗层 的绝缘材料。

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