公开(公告)号：US20170288016A1

公开(公告)日：2017-10-05

申请号：US15627973

申请日：2017-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hoong Shing WONG ,  Min-hwa CHI ,  Tae-Hoon KIM

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced.

公开(公告)号：US20150311083A1

公开(公告)日：2015-10-29

申请号：US14259497

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Changyong XIAO ,  Hoong Shing WONG ,  Deepasree KONDUPARTHI ,  Rohit PAL

IPC: H01L21/28

CPC classification number: H01L29/6653 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7842

Abstract: A method includes providing a gate structure having a dummy gate, a first spacer along a side of the gate. The dummy gate and the spacer are removed to expose a gate dielectric. A second spacer is deposited on at least one side of a gate structure cavity and a top of the gate dielectric. A bottom portion of the second spacer is removed to expose the gate dielectric and the gate structure is wet cleaned.

Abstract translation: 一种方法包括提供具有虚拟栅极的栅极结构，沿栅极侧面的第一间隔物。 去除虚拟栅极和间隔物以露出栅极电介质。 第二间隔物沉积在栅极结构腔的至少一侧和栅极电介质的顶部。 去除第二间隔件的底部以暴露栅极电介质，并且将栅极结构湿式清洁。

公开(公告)号：US20160049495A1

公开(公告)日：2016-02-18

申请号：US14461887

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kristina TREVINO ,  Yuan-Hung LIU ,  Gabriel Padron WELLS ,  Xing ZHANG ,  Hoong Shing WONG ,  Chang Ho MAENG ,  Taejoon HAN ,  Gowri KAMARTHY ,  Isabelle ORAIN ,  Ganesh UPADHYAYA

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L29/4966 ,  H01L29/517

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

Abstract translation: 提供半导体结构和制造方法，其包括例如在半导体衬底上提供栅极结构，所述栅极结构包括多个共形栅极层和设置在多个共形栅极层内的栅极材料; 将多个共形栅极层的一部分凹陷在栅极结构的上表面之下，其中凹入的多个共形栅极层的上表面是共面的; 以及去除所述栅极材料的一部分以便于所述栅极材料的剩余部分的上表面与所述凹入的多个共形栅极层的上表面共面。

公开(公告)号：US20140264489A1

公开(公告)日：2014-09-18

申请号：US13840692

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hoong Shing WONG ,  Min-hwa CHI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7848

Abstract: For the formation of a stressor on one or more of a source and drain defined on a fin of FINFET semiconductor structure, a method can be employed including performing selective epitaxial growth (SEG) on one or more of the source and drain defined on the fin, separating the fin from a bulk silicon substrate at one or more of the source and drain, and further performing SEG on one or more of the source and drain to form a wrap around epitaxial growth stressor that stresses a channel connecting the source and drain. The formed stressor can be formed so that the epitaxial growth material defining a wrap around configuration connects to the bulk substrate. The formed stressor can increase mobility in a channel connecting the defined source and drain.

Abstract translation: 为了在限定在FINFET半导体结构的鳍上的一个或多个源极和漏极上形成应力源，可以采用一种方法，包括在鳍上限定的一个或多个源极和漏极上执行选择性外延生长（SEG） 在源极和漏极中的一个或多个处将散热片与体硅衬底分离开，并且在源极和漏极之一上进一步执行SEG，以形成围绕外延生长应力的环绕，该外延生长应力应力连接源极和漏极的沟道。 形成的应力器可以形成为使得限定缠绕结构的外延生长材料连接到本体基板。 所形成的应力源可以增加连接限定的源极和漏极的通道中的迁移率。

公开(公告)号：US20150187947A1

公开(公告)日：2015-07-02

申请号：US14656649

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min-Hwa CHI ,  Hoong Shing WONG

IPC: H01L29/78 ,  H01L29/22 ,  H01L29/20

CPC classification number: H01L29/7853 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-FinFET and p-FinFET areas. The diamond structures act as the source, drain and channel between the source and drain. The diamond structures of the channel are selectively separated from the fin while retaining the fin connections of the diamond-shaped growth of the source and the drain. Further fabrication to complete the structure may then proceed.

Abstract translation: 制造中的半导体结构包括n-FinFET和p-FinFET。 诸如硅和硅锗的应力诱导材料在n-FinFET和p-FinFET区域的硅散热片的顶部外延生长成天然的菱形结构。 金刚石结构作为源极和漏极之间的源极，漏极和沟道。 通道的金刚石结构与翅片选择性分离，同时保持源极和漏极的菱形生长的翅片连接。 可以进一步完成结构的制造。