SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH
    1.
    发明申请
    SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH 有权
    具有非常数PITCH的次平面半导体结构

    公开(公告)号:US20150380262A1

    公开(公告)日:2015-12-31

    申请号:US14843085

    申请日:2015-09-02

    Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.

    Abstract translation: 公开了使用双材料侧壁图像转印掩模制造翅片结构以实现亚光刻特征图案化的翅片结构和方法。 形成多个翅片的方法包括形成具有第一间距的第一组翅片。 该方法还包括形成与第一组翅片相邻的翅片。 相邻翅片和第一组翅片的最近的翅片具有比第一节距大的第二节距。 第一组翅片和相邻翅片是使用侧壁图像转移过程形成的亚光刻特征。

    Mask free protection of work function material portions in wide replacement gate electrodes
    2.
    发明授权
    Mask free protection of work function material portions in wide replacement gate electrodes 有权
    在宽的替代栅电极中,无功能保护功能材料部分

    公开(公告)号:US09202879B2

    公开(公告)日:2015-12-01

    申请号:US13775988

    申请日:2013-02-25

    Abstract: In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.

    Abstract translation: 在替代栅极方案中,在形成栅极电介质层之后,功函数材料层完全填充窄栅极沟槽,同时不填充宽栅极沟槽。 介电材料层在功函数材料层上沉积并平面化,随后凹入以形成覆盖宽栅极沟槽内的功函数材料层的水平部分的介电材料部分。 使用介电材料部分作为蚀刻掩模的一部分来凹入功函数材料层以形成功函数材料部分。 将导电材料沉积并平坦化以形成栅极导体部分,并且沉积和平坦化介电材料以形成栅极盖电介质。

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