公开(公告)号：US09269621B2

公开(公告)日：2016-02-23

申请号：US14449314

申请日：2014-08-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/311 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

Abstract translation: 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 之后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的 第一条金属线。 形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

公开(公告)号：US20150380262A1

公开(公告)日：2015-12-31

申请号：US14843085

申请日：2015-09-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Marc A. Bergendahl ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/3088 ,  H01L21/2815 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/3086

Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.

Abstract translation: 公开了使用双材料侧壁图像转印掩模制造翅片结构以实现亚光刻特征图案化的翅片结构和方法。 形成多个翅片的方法包括形成具有第一间距的第一组翅片。 该方法还包括形成与第一组翅片相邻的翅片。 相邻翅片和第一组翅片的最近的翅片具有比第一节距大的第二节距。 第一组翅片和相邻翅片是使用侧壁图像转移过程形成的亚光刻特征。

公开(公告)号：US09263388B2

公开(公告)日：2016-02-16

申请号：US14688027

申请日：2015-04-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L21/44

CPC classification number: H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

公开(公告)号：US09202879B2

公开(公告)日：2015-12-01

申请号：US13775988

申请日：2013-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Charles W. Koburger, III ,  Marc A. Bergendahl ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/336 ,  H01L29/40 ,  E21B43/30 ,  E21B47/12

CPC classification number: H01L29/401 ,  E21B43/305 ,  E21B47/122 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211

Abstract: In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.

Abstract translation: 在替代栅极方案中，在形成栅极电介质层之后，功函数材料层完全填充窄栅极沟槽，同时不填充宽栅极沟槽。 介电材料层在功函数材料层上沉积并平面化，随后凹入以形成覆盖宽栅极沟槽内的功函数材料层的水平部分的介电材料部分。 使用介电材料部分作为蚀刻掩模的一部分来凹入功函数材料层以形成功函数材料部分。 将导电材料沉积并平坦化以形成栅极导体部分，并且沉积和平坦化介电材料以形成栅极盖电介质。

公开(公告)号：US09660030B2

公开(公告)日：2017-05-23

申请号：US14473033

申请日：2014-08-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shom Ponoth ,  Marc A. Bergendahl ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC: H01L29/165 ,  H01L21/338 ,  H01L29/08 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/0257 ,  H01L21/02636 ,  H01L21/28008 ,  H01L21/28114 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity.

公开(公告)号：US09263290B2

公开(公告)日：2016-02-16

申请号：US14843085

申请日：2015-09-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Marc A. Bergendahl ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/3088 ,  H01L21/2815 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/3086

Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.