中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.014 seconds)

    Graphene transistor with a sublithographic channel width
    2.
    发明授权
    Graphene transistor with a sublithographic channel width 有权
    具有亚光刻通道宽度的石墨烯晶体管

    公开(公告)号：US09236477B2

    公开(公告)日：2016-01-12

    申请号：US14181832

    申请日：2014-02-17

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jack O. Chu ,  Christos Dimitrakopoulos ,  Eric C. Harley ,  Judson R. Holt ,  Timothy J. McArdle ,  Matthew W. Stoker

    IPC: H01L29/78 ,  H01L29/16 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L29/785 ,  H01L21/0243 ,  H01L21/02447 ,  H01L21/02527 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/66037 ,  H01L29/66795 ,  H01L29/7781

    Abstract: Silicon-carbon alloy structures can be formed as inverted U-shaped structures around semiconductor fins by a selective epitaxy process. A planarization dielectric layer is formed to fill gaps among the silicon-carbon alloy structures. After planarization, remaining vertical portions of the silicon-carbon alloy structures constitute silicon-carbon alloy fins, which can have sublithographic widths. The semiconductor fins may be replaced with replacement dielectric material fins. In one embodiment, employing a patterned mask layer, sidewalls of the silicon-carbon alloy fins can be removed around end portions of each silicon-carbon alloy fin. An anneal is performed to covert surface portions of the silicon-carbon alloy fins into graphene layers. In one embodiment, each graphene layer can include only a horizontal portion in a channel region, and include a horizontal portion and sidewall portions in source and drain regions. If a patterned mask layer is not employed, each graphene layer can include only a horizontal portion.

    Abstract translation: 硅碳合金结构可以通过选择性外延工艺形成为围绕半导体翅片的倒U形结构。 形成平坦化介电层以填充硅 - 碳合金结构之间的间隙。 在平坦化之后，硅 - 碳合金结构的剩余垂直部分构成可以具有亚光刻宽度的硅碳合金翅片。 半导体翅片可以用替换的介质材料翅片代替。 在一个实施例中，采用图案化掩模层，可以在每个硅 - 碳合金散热片的端部周围除去硅 - 碳合金散热片的侧壁。 执行退火以将硅碳合金翅片的表面部分隐藏成石墨烯层。 在一个实施例中，每个石墨烯层可以仅包括沟道区域中的水平部分，并且在源极和漏极区域中包括水平部分和侧壁部分。 如果不使用图案化掩模层，则每个石墨烯层可以仅包括水平部分。

    Method for growing strain-inducing materials in CMOS circuits in a gate first flow
    5.
    发明授权
    Method for growing strain-inducing materials in CMOS circuits in a gate first flow 有权
    在栅极第一流中在CMOS电路中增长应变诱导材料的方法

    公开(公告)号：US08779525B2

    公开(公告)日：2014-07-15

    申请号：US13772401

    申请日：2013-02-21

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    IPC: H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/823828

    Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

    Abstract translation: 在衬底上并入衬底和栅极线的互补金属氧化物半导体（CMOS）电路。 衬底包括n型场效应晶体管（n-FET）区域，p型场效应晶体管（p-FET）区域和设置在n-FET和p-FET区域之间的隔离区域。 栅极线包括n-FET栅极，p-FET栅极和从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极的栅极材料。 第一共形绝缘体覆盖栅极线，并且第二共形绝缘体位于位于p-FET栅极上方的第一共形绝缘体上，而不横向延伸穿过n-FET栅极。 用于产生不同类型应变的应变区形成在蚀刻到衬底的n-FET和p-FET区中的凹槽中。

    METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW
    6.
    发明申请
    METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW 有权
    在门电路第一流程中生长应变诱导材料的方法

    公开(公告)号：US20130161759A1

    公开(公告)日：2013-06-27

    申请号：US13772401

    申请日：2013-02-21

    Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

    Inventor： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    IPC: H01L27/092

    CPC classification number: H01L21/823807 ,  H01L21/823828

    Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

    Abstract translation: 在衬底上并入衬底和栅极线的互补金属氧化物半导体（CMOS）电路。 衬底包括n型场效应晶体管（n-FET）区域，p型场效应晶体管（p-FET）区域和设置在n-FET和p-FET区域之间的隔离区域。 栅极线包括n-FET栅极，p-FET栅极和从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极的栅极材料。 第一共形绝缘体覆盖栅极线，并且第二共形绝缘体位于位于p-FET栅极上方的第一共形绝缘体上，而不横向延伸穿过n-FET栅极。 用于产生不同类型应变的应变区形成在蚀刻到衬底的n-FET和p-FET区中的凹槽中。

Patent Agency Ranking