公开(公告)号：US20200287019A1

公开(公告)日：2020-09-10

申请号：US16296769

申请日：2019-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Hong Yu ,  Man Gu ,  Jianwei Peng ,  Michael Aquilino

IPC: H01L29/66 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A gate structure of the field-effect transistor is arranged over an active region comprised of a semiconductor material. A first sidewall spacer is arranged adjacent to the gate structure. A second sidewall spacer includes a section arranged between the first sidewall spacer and the active region. The first sidewall spacer is composed of a low-k dielectric material.

公开(公告)号：US10340142B1

公开(公告)日：2019-07-02

申请号：US15919119

申请日：2018-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jiehui Shu ,  Pei Liu ,  Jinping Liu

IPC: H01L21/033 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3213

Abstract: At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising vertically aligned gates, metal hard masks, and nitride regions. The semiconductor device may contain a semiconductor substrate; a gate disposed on the semiconductor substrate; a metal hard mask vertically aligned with the gate; a nitride region vertically aligned with the gate and the metal hard mask; and source/drain (S/D) regions disposed in proximity to the gate.

公开(公告)号：US20190326408A1

公开(公告)日：2019-10-24

申请号：US16458056

申请日：2019-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Daniel Jaeger ,  Haigou Huang ,  Veeraraghavan Basker ,  Christopher Nassar ,  Jinsheng Gao ,  Michael Aquilino

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/321 ,  H01L27/092 ,  H01L29/417 ,  H01L21/28

Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

公开(公告)号：US20190097015A1

公开(公告)日：2019-03-28

申请号：US15716287

申请日：2017-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Daniel Jaeger ,  Haigou Huang ,  Veeraraghavan Basker ,  Christopher Nassar ,  Jinsheng Gao ,  Michael Aquilino

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/321

CPC classification number: H01L29/4933 ,  H01L21/02425 ,  H01L21/2257 ,  H01L21/28052 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

公开(公告)号：US10930549B2

公开(公告)日：2021-02-23

申请号：US16573209

申请日：2019-09-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Chih-Chiang Chang ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Mitchell Rutkowski ,  Haigou Huang ,  Huy Cao

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

公开(公告)号：US10522639B2

公开(公告)日：2019-12-31

申请号：US16458056

申请日：2019-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Daniel Jaeger ,  Haigou Huang ,  Veeraraghavan Basker ,  Christopher Nassar ,  Jinsheng Gao ,  Michael Aquilino

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/225 ,  H01L21/321 ,  H01L27/092 ,  H01L29/417 ,  H01L21/8238

Abstract: At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

公开(公告)号：US20190280114A1

公开(公告)日：2019-09-12

申请号：US15919079

申请日：2018-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Xusheng Wu ,  Haigou Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.

公开(公告)号：US20200335591A1

公开(公告)日：2020-10-22

申请号：US16386363

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Aquilino ,  Daniel Jaeger ,  Naved Siddiqui ,  Jessica Dechene ,  Daniel J. Dechene ,  Shreesh Narasimha ,  Natalia Borjemscaia

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/311 ,  H01L21/033 ,  H01L29/40

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.

公开(公告)号：US10460986B2

公开(公告)日：2019-10-29

申请号：US15882291

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Chih-Chiang Chang ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Mitchell Rutkowski ,  Haigou Huang ,  Huy Cao

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

公开(公告)号：US10325819B1

公开(公告)日：2019-06-18

申请号：US15920303

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Jessica Dechene ,  Huy Cao ,  Mitchell Rutkowski ,  Haigou Huang

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/768 ,  H01L21/306 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3105

Abstract: At least one method, apparatus and system disclosed herein involves forming trench silicide region contact. A plurality of fins are formed on a semiconductor substrate. An epitaxial (EPI) feature is formed at a top portion of each fin of the first portion over a first portion of the fins. A gate region is formed over a second portion of the fins. A trench is formed in a portion of the gate region. A void is formed adjacent the a portion of the gate region. A first silicon feature is formed in the trench. A second silicon feature is formed in the void. Subsequently, a replacement metal gate (RMG) process is performed in the gate region. A TS cut region is formed over the trench. The first silicon feature and the second silicon feature are removed. A metallization process is performed in the void to form a contact.