公开(公告)号：US20160260742A1

公开(公告)日：2016-09-08

申请号：US15156506

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil JACOB ,  Kangguo CHENG ,  Bruce DORIS ,  Nicolas LOUBET ,  Prasanna KHARE ,  Rama DIVAKARUNI

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/308 ,  H01L21/02 ,  H01L21/84 ,  H01L21/306

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供了由这些方法形成的方法和半导体结构，其有助于制造半导体鳍结构。 所述方法包括例如：提供具有在衬底上延伸的至少一个半导体鳍片的晶片; 将所述半导体鳍片的一部分转换成隔离层，所述隔离层将所述半导体鳍片的半导体层与所述衬底分离; 并且在半导体鳍片的第一鳍片区域中形成第一结构类型的翅片装置，并且在半导体鳍片的第二鳍片区域中形成第二结构类型的鳍片装置（ s），其中第一架构类型和第二架构类型是不同的fin设备架构。

公开(公告)号：US20150024572A1

公开(公告)日：2015-01-22

申请号：US13945445

申请日：2013-07-18

Applicant: INTERNATIONAL BUSINESS MACHIES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Ajey P. JACOB ,  Kangguo CHENG ,  Bruce B. DORIS ,  Nicolas LOUBET ,  Prasanna KHARE ,  Ramachandra DIVAKARUNI

IPC: H01L21/762

CPC classification number: H01L21/76243 ,  H01L21/302 ,  H01L21/76267 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L27/1211 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor fabrication methods are provided which include facilitating fabricating semiconductor fin structures by: providing a wafer with at least one fin extending above a substrate, the at least one fin including a first layer disposed above a second layer; mechanically stabilizing the first layer; removing at least a portion of the second layer of the fin(s) to create a void below the first layer; filling the void, at least partially, below the first layer with an isolation material to create an isolation layer within the fin(s); and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the fin(s), and a fin device(s) of a second architectural type in a second fin region of the fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供了半导体制造方法，其包括：通过以下方式制造半导体鳍片结构：提供具有在衬底上延伸的至少一个翅片的晶片，所述至少一个鳍片包括设置在第二层上方的第一层; 机械稳定第一层; 去除所述翅片的所述第二层的至少一部分以在所述第一层下面形成空隙; 至少部分地用隔离材料填充第一层下面的空隙，以在散热片内产生隔离层; 并且在翅片的第一翅片区域中形成第一结构类型的翅片装置，并且在翅片的第二翅片区域中形成第二结构类型的翅片装置， ，其中第一种架构类型和第二种架构类型是不同的鳍设备架构。

公开(公告)号：US20160190304A1

公开(公告)日：2016-06-30

申请号：US14588221

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pierre MORIN ,  Kangguo CHENG ,  Jody FRONHEISER ,  Xiuyu CAI ,  Juntao LI ,  Shogo MOCHIZUKI ,  Ruilong XIE ,  Hong HE ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7849

Abstract: A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.

Abstract translation: 具有基本上无缺陷的SiGe应变松弛缓冲层的改性硅衬底适用于构建高性能CMOS FinFET器件的基础。 可以通过切割或分割应变的外延膜来形成基本上无缺陷的SiGe应变松弛缓冲层，使得薄膜段的边缘经历弹性应变弛豫。 当片段足够小时，整个膜被松弛，使得膜基本上没有位错缺陷。 一旦形成了基本上无缺陷的应变松弛缓冲层，则可以从松弛的SRB层外延生长应变通道层。 然后将应变通道层图案化以产生用于FinFET器件的鳍片。 在一个实施例中，形成双应变通道层 - 用于NFET器件的拉伸应变层，以及用于PFET器件的压缩应变层。

公开(公告)号：US20190081155A1

公开(公告)日：2019-03-14

申请号：US15703221

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Kangguo CHENG ,  Nicolas LOUBET ,  Xin MIAO ,  Pietro MONTANINI ,  John ZHANG ,  Haigou HUANG ,  Jianwei PENG ,  Sipeng GU ,  Hui ZANG ,  Yi QI ,  Xusheng WU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier.