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    ADJUSTING CONFIGURATION OF A MULTIPLE GATE TRANSISTOR BY CONTROLLING INDIVIDUAL FINS
    2.
    发明申请
    ADJUSTING CONFIGURATION OF A MULTIPLE GATE TRANSISTOR BY CONTROLLING INDIVIDUAL FINS 审中-公开
    通过控制个人FINS调整多个门控晶体管的配置

    公开(公告)号：US20130306967A1

    公开(公告)日：2013-11-21

    申请号：US13869162

    申请日：2013-04-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jan Hoentschel ,  Robert Mulfinger ,  Vassilios Papageorgiou

    IPC: H01L23/58

    CPC classification number: H01L23/58 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a sophisticated semiconductor device, FINFET elements may be provided with individually accessible semiconductor fins which may be connected to a controllable interconnect structure for appropriately adjusting the transistor configuration, for instance with respect to current drive capability, replacing defective semiconductor fins and the like. Consequently, different transistor configurations may be obtained on the basis of a standard transistor cell architecture, which may result in increased production yield of highly complex manufacturing strategies in forming non-planar transistor devices.

    Abstract translation: 在复杂的半导体器件中，FINFET元件可以设置有单独可访问的半导体鳍片，其可以连接到可控制的互连结构，以适当地调整晶体管配置，例如关于电流驱动能力，替换有缺陷的半导体鳍片等。 因此，可以在标准晶体管单元架构的基础上获得不同的晶体管配置，这可能导致在形成非平面晶体管器件时高度复杂的制造策略的生产成本增加。

    Adjusting configuration of a multiple gate transistor by controlling individual fins
    4.
    发明授权
    Adjusting configuration of a multiple gate transistor by controlling individual fins 有权
    通过控制单个散热片来调整多栅极晶体管的配置

    公开(公告)号：US09035306B2

    公开(公告)日：2015-05-19

    申请号：US13869162

    申请日：2013-04-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jan Hoentschel ,  Robert Mulfinger ,  Vassilios Papageorgiou

    IPC: H01L23/58 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L23/58 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a sophisticated semiconductor device, FINFET elements may be provided with individually accessible semiconductor fins which may be connected to a controllable interconnect structure for appropriately adjusting the transistor configuration, for instance with respect to current drive capability, replacing defective semiconductor fins and the like. Consequently, different transistor configurations may be obtained on the basis of a standard transistor cell architecture, which may result in increased production yield of highly complex manufacturing strategies in forming non-planar transistor devices.

    Abstract translation: 在复杂的半导体器件中，FINFET元件可以设置有单独可访问的半导体鳍片，其可以连接到可控制的互连结构，以适当地调整晶体管配置，例如关于电流驱动能力，替换有缺陷的半导体鳍片等。 因此，可以在标准晶体管单元架构的基础上获得不同的晶体管配置，这可能导致在形成非平面晶体管器件时高度复杂的制造策略的生产成本增加。

    STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE
    5.
    发明申请
    STRAIN ENHANCEMENT IN TRANSISTORS COMPRISING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR ALLOY BY CREATING A PATTERNING NON-UNIFORMITY AT THE BOTTOM OF THE GATE ELECTRODE 有权
    通过在门电极底部形成图案非均匀性来包含嵌入式应变诱导半导体合金的晶体管中的应变增强

    公开(公告)号：US20140339604A1

    公开(公告)日：2014-11-20

    申请号：US14447830

    申请日：2014-07-31

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Stephan Kronholz ,  Markus Lenski ,  Vassilios Papageorgiou

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L27/092

    CPC classification number: H01L29/7848 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51

    Abstract: A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less. A strain-inducing semiconductor alloy is embedded in the semiconductor region laterally adjacent to the bottom portion of the gate electrode structure, and drain and source regions are at least partially positioned in the strain-inducing semiconductor alloy.

    Abstract translation: 半导体器件包括晶体管的栅极电极结构，栅极电极结构位于半导体区域之上并具有包括高k介电材料的栅极绝缘层，位于栅极绝缘层上方的含金属盖材料， 以及位于含金属盖材料上方的栅电极材料。 栅电极结构的底部具有第一长度，并且栅电极结构的上部具有与第一长度不同的第二长度，其中第一长度为约50nm或更小。 应变诱导半导体合金嵌入在与栅电极结构的底部相邻的半导体区域中，并且漏极和源极区域至少部分地位于应变诱导半导体合金中。

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